Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

Abstract: A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the device is retrieved from multiple addresses on the uncached device to avoid unnecessary waits cycles in the processor.

Abstract: An error-correcting partial latch stage includes a first pass gate having an input for receiving a data input signal, an output, and a control node for receiving a control signal, a second pass gate having an input coupled to the output of the first pass gate, an output for providing a data output signal, and a control node for receiving the control signal, an inverter having an input coupled to the output of the first pass gate and an output; and a correcting inverter stage having a first input coupled to the output of the inverter, and second and third inputs for receiving voting signals from adjacent error-correcting latch stages, and an output coupled to the output of the second pass gate. A full latch stage includes three interconnected partial latch stages. The full latch stage has a high degree of immunity from SEU events and from on-chip noise coupling.

Abstract: An integrated circuit comprising a plurality of functional modules and interconnected via a packet router for conveying request and response packets is described. Transactions involve the dispatch of request packets and receipt of corresponding response packets. Each packet conveys a number of transaction attributes which can control how the packet is managed by control circuitry which controls the flow of packets on the packet router. For example the transaction attributes can include a transaction number, a grouping indicator, a priority indicator and a post indicator.

Abstract: Data retention of a ferroelectric transistor is extended by intecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: A high availability, high reliability storage system that leverages rapid advances in commodity computing devices and the robust nature of internetwork technology such as the Internet. A system of parity distribution in accordance with the present invention allows for greater fault tolerance and levels of storage efficiency than possible with conventional RAID (levels 0-5) paradigms. Data can be recovered or made available even in the case of loss of N, N+1, or more devices or storage elements over which stripes of the data set have been distributed or partitioned. The present invention provides a parity distribution that can be used to distribute data stored in a single storage device or across multiple connected or otherwise networked devices.

Abstract: The present invention describes a method and system for providing cluster replicated checkpoint services. In particular, the method provides cluster replicated checkpoint services for replicas of a checkpoint in a cluster. The cluster includes a first node and a second node, which are connected to one another via a network. The replicas include a primary replica and a secondary replica. The method includes managing the checkpoint that contains checkpoint information, and creating the primary replica in a memory of the first node. The primary replica contains first checkpoint information. The method also includes updating the primary replica so that the first checkpoint information corresponds to the checkpoint information, creating the secondary replica that contains second checkpoint information in a memory of the second node, and updating the secondary replica so that the second checkpoint information corresponds to the checkpoint information.

Abstract: A method and apparatus for routing frames through a fiber channel fabric to make the most efficient possible use of redundant inter-switch links between neighboring switches. The inter-switch links may have different bandwidths. The flow between adjacent switches is monitored to determine various local usage statistics and periodically adjust routing tables to move data flows from congested links to lightly loaded links.

Abstract: A bandgap reference circuit includes a current-voltage mirror circuit having first, second, third, and fourth nodes, a transistor having a current path coupled between a source of supply voltage and the first node, a current mirror portion having an input coupled to the first node and a control terminal coupled to the fourth node, a serially coupled first resistor and first diode coupled between the output of the current mirror portion and ground, a serially coupled second resistor and second diode coupled between the third node and ground, a third diode coupled between the second node and ground, and a differential amplifier having a first input coupled to the fourth node, a second input coupled to the output of the current mirror portion for generating a bandgap reference voltage, and an output coupled to the gate of the transistor.

Abstract: The present invention includes an integrated circuit that can use a high-frequency timing reference generator from a high-speed serial interface to provide the clocking and timing requirements for the integrated circuit. The timing mechanism in the present invention obviates the need for phase locked loop (PLL) macrocells to provide timing reference and timing signals in the IC. The ICs of the present invention are preferably used as disk drive integrated circuits that include DSP, memory, data path controllers, data interfaces, custom macrocells, and DSP peripherals. The high-speed serial interface is preferably a Serial ATA (SATA), Universal Serial Bus (USB), Fiber Channel, or Serial Attached SCSI (SAS), among others.

Abstract: A system and method for unorchestrated determination of data sequences using “sticky byte” factoring to determine breakpoints in digital sequences such that common sequences can be identified. Sticky byte factoring provides an efficient method of dividing a data set into pieces that generally yields near optimal commonality. This is effectuated by employing a rolling hashsum and, in an exemplary embodiment disclosed herein, a threshold function to deterministically set divisions in a sequence of data. Both the rolling hash and the threshold function are designed to require minimal computation. This low overhead makes it possible to rapidly partition a data sequence for presentation to a factoring engine or other applications that prefer subsequent synchronization across the data set.

Abstract: A method, system, and computer program product for accessing server resources by a client communicating control data to a server. A context object is associated to the control data. The context object includes methods for recording within the context object a set of properties identifying the client. A request packet is created from the control data and the context object. The request packet is transmitted to the server. The context object is passed to at least one method on the server. The method uses the context object to access the server resources.

Abstract: The present invention relates a Pulse Width Modulation (PWM)/linear driver for an electromagnetic load by a bridge circuit of the type having a signal input and a signal output and at least two conduction control inputs for driving a voice coil motor in a linear mode and in a pulse width modulation. The bridge circuit is driven by a PWM converter coupled to one of said two control inputs and by a linear amplifier coupled to the other of said two control inputs.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relatively large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is formed. A number of shallow trenches are formed between the active regions one or more of which may constitute an alignment mark. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial reverse active mask exposes a portion of the oxide layer over the large active area and over the alignment mark. The oxide layer of each large active region and the alignment mark is removed. The partial reverse active mask is removed. The oxide layer is planarized.

Abstract: Data retention of a ferroelectric transistor is extended by injecting holes or electrons into the ferroelectric transistor when power is removed. The ferroelectric FET has a mechanism to trap charge in a buffer dielectric layer or in the ferroelectric layer sandwiched between a top electrode and a silicon substrate. The state of polarization is detected before power is removed from the ferroelectric FET. Charge is injected into the ferroelectric FET to produce a first threshold voltage when a first polarization state is determined before power is removed. Charge is removed from the ferroelectric FET to produce a second threshold voltage when a second polarization state is determined before power is removed. When the ferroelectric FET is powered up again, the state of charge injected is determined. The ferroelectric FET is then polarized to correspond to a first threshold voltage when the charge state corresponding to the first threshold is determined.

Abstract: A circuit and method reduces the number of nodes that must be forced during a standby mode when using clocked latches. The circuit and method can be used for half-cycle latches and full cycle latches in conjunction with alternate power-gated circuitry, even when many stages are cascaded in a pipeline structure. The data state on a single forcing node can be passed through one or more cascaded latch stages as well as through additional circuitry. By forcing latch transmission gates to be conductive during standby mode, multiple stages can be set to a specific state, as determined by an earlier stage being set by a forcing transistor. A clock generation. circuit and method is also provided for controlling transmission gates within the latches.

Abstract: A latch circuit and method of operation improves the performance of an integrated circuit memory by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information.

Abstract: A bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO3, wherein the PZT film includes pinholes, with a pinhole density of about 17 &mgr;m2 or less.