Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory having a large aspect ratio serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. The memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate and single-ended which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory, which reduces the capacitance of the lines.

Abstract: A search coprocessor card for attachment to a computer system has an interface to a host processor of the computer system and a processor. The processor has memory for its program and data, and is coupled to one or more search engine devices. Each of the search engine devices is in turn coupled to a memory for holding key tables, and is capable of searching the key tables for matching entries.

Abstract: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Abstract: A circuit and method for an integrated circuit memory incorporates a look-ahead function where refresh commands are presented to the device at least one cycle before actual internal refresh operations occur. Active cycles are executed on the same clock as the external command is applied. Active commands are unaltered and are executed on the same clock cycle as the occurrence of the active command. Active commands can be executed immediately without waiting to determine if the row address latch is to be sourced externally or internally.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: A data path decoding technique and architecture for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (“DRAM”) arrays provides an effective second level of decoding resulting in a need for routing fewer column select lines to the sense amplifiers as compared with existing designs while concomitantly providing for shortened local data lines resulting in less undesired resistance and capacitance. The technique and architecture of the present invention requires no additional on-chip area to that required by existing designs and adds no new gate delays or pass gates to the critical read data or write data paths. This is effectuated by the incorporation of an address function with the read/write enable (“RWEN”) or separate read enable (“REN”) and write enable (“WEN”) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is provided.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data +½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.

Abstract: A system and method is provided for placing gate capacitors, or other performance enhancing electrical components, in an under-utilized standard cell region. The present invention is a layout design tool that allows the designed to automatically intersperse capacitor filler cells around standard cell logic. The present invention includes creating a region, allocated to the particular standard cell, which has (either by intention or situation) low utilization. The design tool of the present invention can also be used to intentionally under-utilize various functional blocks in order to create areas that can be filled with cells containing gate capacitors. The standard cells may or may not be associated with surrounding logic. The place and route filler cells are redefined to include gate capacitors using abutment rules compatible with the standard cells.

Abstract: A method for searching a computer directory database is disclosed. The method compares a first and second filename strings, the comparing operating in reverse order, from the end of the strings towards the beginning until either the entirety of the strings has been compared or a mismatch has been found.

Abstract: A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A lead compensator determines a compensated command to compensate for an admittance function of the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Abstract: A method and system that manage upgrades in a high-availability computer system by viewing the upgrade process as driving the system between a succession of stable configurations. The mechanism used by a described embodiment is an availability manager that is capable of ascertaining the state of each component and driving it toward a goal state by driving toward a succession of desired stable configurations. A high-level orchestration agent instructs the availability manager when a stable configuration has been reached and it is time to drive toward a next stable configuration.

Abstract: Network address (e.g. IP address) allocation under first and second protocols (e.g. RADIUS and DHCP) is achieved using a directory service. A common network address pool is maintained under the control of a directory service. The directory service allocates network addresses in response to requests. The directory service also maintains a record of network address allocation to users, which can be achieved by storing a network address allocated to a user at the user's entry in the directory. Thus, for example, IP address allocation under RADIUS and DHCP can be unified using a common address pool and mappings between IP addresses and the user/hosts information in an ISO/CCITT X.500 based directory service using LDAP.

Abstract: An automatic delay technique for early “read” and “write” memory access operations in synchronous dynamic random access memory (“SDRAM”) devices and those integrated circuit devices employing embedded SDRAM arrays. A circuit and method is provided which controls the internal column select (“Yi”) and data signals such that the column address strobe (“/CAS”) signal is allowed to go “active” in advance of that otherwise possible in conjunction with conventional SDRAM arrays. In an exemplary embodiment, the column select signals (“read” or “write”) are delayed until either the corresponding, pre-decoded column address signal or the respective column clock signal is valid, whichever occurs later.

Abstract: A method for scoring queued frames 18 for selective transmission through a switch (12) includes providing one or more switches in a fibre channel fabric, particularly one or more fibre channel switches (12′). The method includes assigning an initial score (20) to the content (42) of the one or more frames (18) of data (26). The initial score (20) is adjusted by one or more alternative score components to determine one or more adjusted scores (22). The adjusted scores (22) are compared. The method also provides for selecting frames (18) having the highest adjusted scores (22), and transmitting through the switches (12) the frames (18) having the highest adjusted scores (22).

Abstract: A method and apparatus including a plurality of data processing units. A plurality of memory banks having a shared address space are coupled to the processors by a crossbar coupling to enable reading and writing data between the processors and memory banks. A unidirectional network couples the memory banks and the processors to enable cache coherency messages to be transmitted from the memory to the processors. A plurality of semaphore registers are implemented within the shared address space of the memory banks wherein the semaphore registers are accessible by the processors through the crossbar coupling.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: An arbitration method and circuit for control of double data rate (“DDR”) dynamic random access memory (“DRAM”) device first-in, first-out (“FIFO”) registers which allows the data path of the device to be functional over a wider range of system clock and delay locked loop (“DLL”) clock signal skews. By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, it then attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast, that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow.

Abstract: The invention provides a high-speed interface that transfers servo position data from the read channel integrated circuit to the drive control integrated circuit or another integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data which speeds up the data transfer. Examples of servo position data include high-resolution servo position data and coarse-resolution servo position data. A read channel integrated circuit transfers the user data and the high-resolution servo position data to a data bus, such as an NRZ bus. The data bus transfers the user data and the high-resolution servo position data to another integrated circuit, such as a drive control integrated circuit. The other integrated circuit receives the user data and the high-resolution servo position data from the data bus.

Abstract: A method, and a system for implementing such method, for use in a magnetic disk storage system for compensating for variation in spin speed of a data storage media from a nominal or design spin speed. The method includes providing the nominal spin speed for the data storage media in the particular magnetic disk storage system and then measuring the actual spin speed of the data storage media. In one preferred embodiment, the spin speed measurement is completed by measuring the time from one servo position field to the next sequential servo position field in a track on the data storage media. Next, the present spin speed variation is determined by comparing the measured spin speed with the nominal spin speed. A correction factor is calculated based on the spin speed error and applied to at least one data transfer parameter, such as channel reference frequency or read/write gate assertion timing, prior to a subsequent data transfer process (i.e., a read or a write operation).