Abstract: A cache system and a method for an extent-based cache memory design are disclosed. The method Includes providing a storage device and a host device where each device is in communication with the memory and creating an extent record associated with the memory. A storage device access request is received from the host device and at least one state field value in the extent record is changed in response to the access request from the host device. The size of an extent associated with the extent record and allocated within the memory may be based on the access request and any additional speculative data. The at least one state field value may be selected from the group consisting of extent size, valid count, hit count, and dirty count. The storage device may be implemented as an intelligent hard disk drive and the memory may be implemented by random access memory (RAM).

Abstract: A pre-biased voltage level shifting circuit of especial applicability with respect to those integrated circuit devices requiring a technique for converting circuit operation between differing power supply levels. In a representative embodiment, the circuit utilizes feedback to make the switching transistors faster to thereby increase the speeds of the level translation of signals based upon two different power supplies.

Abstract: A method of demand based retrieval of a data file including pages of data, in a network system having a remote host system interconnected to at least one local host system via a first communication link, and one or more end-user systems interconnected to the local host system via a second communication link. A cache buffer is maintained in the local host system for storing a plurality of data pages. Upon receiving a request from an end-user system for the data file, the cache buffer is checked to determine if one or more data pages currently referenced by the request are available therein. If so, one or more of the available data pages are transmitted from the cache buffer to the end user system. Otherwise, the referenced pages are retrieved from the remote host system to the local host system via the first communication link, stored in the cache buffer in the local host system, and transmitted to the end-user system via the second communication link.

Abstract: A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.

Abstract: A computerized method for automatically analyzing a core file created by a computer system after an unexpected interrupt. The packages installed on the computer system are determined and patch files of descriptive data for previously identified patches are accessed to create a patch search set including patches configured for use with the installed packages. Patches in the patch search set are scored by assigning points to each patch based on scoring rules, e.g., searching the patch descriptive data for matches between portions of the patch descriptive data and portions of the core file, including bug descriptions. For UNIX™-based kernel core files, the scoring rules involve creating search criteria based on panic types and on panic metric data gathered from the core file. A detailed patch search report is created providing recommendations for each of the scored patches based on the assigned score and identifying patches for installation.

Abstract: Circuits and methods for generating a reset signal are disclosed. A reset driver circuit receives a reset signal from a circuit, e.g., a reset generator and an input signal indicative of a required characteristic of a reset signal for a second circuit. The reset driver compares a characteristic of the reset signal with the input signal indicative of a required characteristic of a reset signal for a second circuit and generates an output signal that includes the required characteristics of the reset signal for a second circuit. A reset driver circuit may be placed in a communication path between a conventional reset generator and a second circuit that requires a reset signal.

Abstract: A power driver for driving a signal on a load using voltage-mode driver. A system processor generates commands indicating a programmed drive signal desired from the voltage-mode driver. A VBEMF compensator determines a compensated command to compensate for the back electromotive force voltage produced by the load. The compensated commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the compensated command.

Abstract: Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.

Abstract: A method, system and apparatus for generating and optimizing native code in a runtime compiler from a group of bytecodes presented to the compiler. The compiler accesses information that indicates a likelihood that a class will be a particular type when accessed by the running program. Using the accessed information, the compiler selects a code generation method from a plurality of code generation methods. A code generator generates optimized native code according to the selected code generation method and stores the optimized native code in a code cache for reuse.

Abstract: A mechanism for managing a plurality of profile data structures where each profile data structure comprising a hierarchical structure of attributes. The mechanism includes a core profile service engine having a number of predefined built-in functions. A first pluggable interface within the core profile service supports runtime binding to remote protocol adapterso. A second pluggable interface within the core profiling service supports runtime binding to external datastore plug-ins. A third pluggable interface within the core profiling service supports runtime binding to external service plug-ins where the external service plug-ins provide functions for manipulating profile data structures in addition to built in functions provided by the core profile service.

Abstract: A head position control system for a dual stage actuation disk drive system. A feedback system is provided for modifying a primary and a secondary input command signal to produce primary and secondary error signals. A controller receives the primary error signal and transmits primary actuator arm positioning information to the primary actuator. A secondary controller receives the secondary error signal and transmits secondary actuator arm positioning information to the secondary actuator. The feedback system creates a position error signal (PES) using information from servo wedges and runout information and the PES is used to produce the secondary error signal. The feedback system produces a reconstructed error signal including angular position information for the primary actuator arm by processing a back electromotive force signal from the primary actuator. The primary error signal is produced by modifying the primary input signal with the reconstructed error signal.

Abstract: A non-clocked data-in path in an integrated circuit device incorporating a random access memory array allows data written to the array to ripple through to all banks all the way up to the local write circuitry. This allows for the fastest writes possible to the array since there are no additional clocking registers to slow down the data flow.

Abstract: A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (“I/O”) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Abstract: An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chip Y-clock signal (column address select) without the need to provide separate circuits. In those devices having multiple DQS inputs, any skew between DQS pins is allowed as long as no one DQS pin violates the DQS-to-clock (“DQS-CLK”) skew requirements. The circuit and method of the present invention also allows a write to occur at command +2 cycles (last data + ½). Functionally, both rising and falling data (i.e., data on the rising and falling edges of DQS) is captured by the DQS inputs and presented in parallel to the chips internal write path and data is passed on the falling edge of DQS.

Abstract: An upper stem diameter measurement (“USDM”) and basal area determination device for timber cruising operations incorporates a viewing window in which are projected variable, visual brackets for manual alignment by the user, or automatic setting under processor section control, with the left and right sides of a target tree stem or trunk. The device further includes a built-in inclinometer such that computations of height and stem diameter can be automatically adjusted depending on the user's line of sight with respect to a horizontal plane. In a preferred embodiment, a user actuatable keypad is provided for inputting data, such as a desired operational mode, a specified basal area factor and the like, a user viewable display as well as control buttons for adjusting the visual brackets and indicating an acceptance of various of the device parameters and operational characteristics.

Abstract: A method for identifying software executing on a computer system from a memory image defining at a particular time a state of the executing software. The method includes populating a comparison file for the computer system with executable signatures. The executable signatures correspond to preselected executables that can be run on the computer system, such as kernel software, and include version identifying information. Executables are located in the received memory image and are then processed to generate comparison information. The comparison information is compared to the version identifying information to identify software. Executable text segments in the preselected executables are isolated, and offset, size, and checksum are determined for inclusion in the executable signature. The executable text segments in the memory image are isolated and a checksum determined. The checksum information is then compared to achieve matches and to accurately identify software versions running on the computer system.

Abstract: An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.

Abstract: A VCM power driver having an input for receiving an external supply voltage VDD. A voltage-mode driver is coupled to the power supply voltage and generates a drive signal to a load. A system processor generates commands indicating a programmed voltage output desired from the voltage-mode driver. A comparator compares VDD to a reference voltage to generate an error signal. A combination mechanism generates a modified command using the error signal. The modified commands are coupled to the voltage-mode driver, such that the voltage-mode driver generates a voltage output based upon the modified command.

Abstract: A continuous automatic calibration system and apparatus using a delta-sigma modulation technique. A first time duration is set. The first time duration is a length of time in terms of clock counts for a calibration procedure. Then, a second time duration occurring during the first time duration is measured. The second time duration is a length of time in terms of clock counts that a counter is operational. A multiplying factor is determined by dividing the first time duration by the second time duration.

Abstract: A high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages. In accordance with the technique of the present intention, the problems inherent in the amount of on-chip die area consumed and speed degradation of prior art circuit implementations are overcome by furnishing a substantially direct current voltage VHVP to the gate of a first transistor of a series connected thin gate oxide pair wherein VHVP≦VDSMAX (the maximum gate-to-source voltage of the first transistor) and VHVP≦VDSMAX+Vt (the maximum drain-to-source voltage of the second transistor plus the threshold voltage of the first transistor).