Patents Represented by Attorney, Agent or Law Firm William J. Stoffel
  • Patent number: 7363236
    Abstract: A method, apparatus and system are provided for determining the price of a reticle set. The system retrieves information related to a specific reticle set from various data sources (e.g., data bases) and determines a price for the reticle set. An example embodiment of the method of the invention for calculating a price of a reticle set comprises: a) receiving customer information for the reticle set and storing the customer information; b) receiving sales order data for the reticle set and storing the sales order data; c) retrieving layer information for the reticle set and storing the layer information; d) retrieving cost data for the layer information for the reticle set and storing the cost data; e) determining the price of the reticle set using the layer information, the sales order data, and the cost data; and storing the price of the reticle set; and f) outputting the price of the reticle set.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: April 22, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Danchai Kochpatcharin, Jennifer Su Ping Teong, Yee Hwee Phuan, Elizabeth Lim, Kenneth Zoo Khean Ngeow, Winson Yong
  • Patent number: 7294241
    Abstract: A method of sputtering a Ta layer comprised of alpha phase Ta on a Cu layer. An embodiment includes a Ta sputter deposition on a Cu surface at a substrate temperature less than 200° C. Another embodiment has a pre-cooling step at a temperature less than 100° C. prior to Ta layer sputter deposition. In another non-limiting example embodiment, a pre-clean step comprising an inert gas sputter is performed prior to the tantalum sputter. Another non-limiting example embodiment provides a semiconductor structure comprising: a semiconductor structure; a copper layer over the semiconductor structure; a tantalum layer on the copper layer; the tantalum layer comprised alpha phase Ta; a metal layer on the tantalum layer.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: November 13, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chim Seng Seet, Bei Chao Zhang, San Leong Liew, John Sudijono, Lai Lin Clare Yong
  • Patent number: 7291550
    Abstract: A example method of forming of a contact hole by removing residue and oxide spacer beside a nitride spacer after a CF containing etch. We provide a gate structure with nitride spacers on the sidewalls of the gate. We provide a dielectric layer (oxide) over the substrate and gate structure. We form a contact photoresist pattern over the oxide dielectric layer. We etch the oxide dielectric layer using fluorocarbons (CxFy) to form contact openings and residual spacer. The photoresist is striped. Preferably, a NF3 and N2 and H2 plasma treatment is performed to deposit a byproducts layer over the residual spacer. The byproducts layer and residual spacer are removed preferably using one of the following processes: (1) heat (2) DI rinse or (3) IR or UV radiation.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: November 6, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Jeong-Ho Kim
  • Patent number: 7288366
    Abstract: A reticle structure and a method of forming a photoresist profile on a substrate using the reticle having a multi-level profile. The reticle comprises (1) a transparent substrate, (2) a partially transmitting 180 degree phase shift film overlying predetermined areas of the transparent substrate to transmit approximately 20 to 70% of incident light, and (3) an opaque film overlying the predetermined areas of the partially transmitting 180 degree phase shift film. The method comprises the following steps: a) depositing a photoresist film over the substrate; b) directing light to the photoresist film through the reticle, and c) developing the photoresist film to form an opening in the resist layer where light only passed thru the substrate, and to remove intermediate thickness of the photoresist film, in the areas where the light passed through the partially transmitting 180 degree phase shift film. In an aspect, the photoresist film is comprised of a lower photoresist layer and an upper photoresist layer.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: October 30, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sia Kim Tan, Qun Ying Lin, Soon Yoeng Tan, Huey Ming Chong
  • Patent number: 7276797
    Abstract: A structure and method for an improved a bond pad structure. A top wiring layer and a top dielectric (IMD) layer over a semiconductor structure are provided. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. A buffer opening is formed in the buffer dielectric layer exposing at least of portion of the top wiring layer. A barrier layer is formed over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. The conductive buffer layer is planarized to form a buffer pad in the buffer opening. A passivation layer is formed over the buffer pad and the buffer dielectric layer. A bond pad opening is formed in the passivation layer over at least a portion of the buffer pad. A bond pad support layer is formed over the buffer pad and the buffer dielectric layer. A bond pad layer is formed over the bond pad support layer.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: October 2, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Zhang Fan, Zhang Bei Chao, Liu Wuping, Chok Kho Liep, Hsia Liang Choo, Lim Yeow Kheng, Alan Cuthbertson, Tan Juan Boon
  • Patent number: 7256084
    Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: August 14, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh
  • Patent number: 7256112
    Abstract: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: August 14, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Yung Fu Chong, Dong Kyun Sohn, Liang Choo Hsia
  • Patent number: 7253483
    Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: August 7, 2007
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Yisuo Li, Xiaohong Jiang, Francis Benistant
  • Patent number: 7202133
    Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: April 10, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
  • Patent number: 7202140
    Abstract: A method for forming a semiconductor structure having devices formed on both sides. A first substrate and a second substrate are provided. The first substrate is preferably comprised of Ge. The second substrate is preferably comprised of silicon. We form a first dielectric layer over the first substrate. We form a first insulating layer over the second substrate. We bond the first dielectric layer and the first dielectric layer to form a first structure. The first structure comprised of the first substrate, an insulation layer (combined first dielectric and first insulating layers) and the second substrate. We reduce the thickness of the first substrate. We form via plugs through the first substrate and the insulation layer and at least partially through the second substrate. We form first active devices on the surface of the first substrate. We form a first capping layer over the first active devices and the first substrate. We reduce the thickness of the second substrate to expose the via plugs.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: April 10, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Chew Hoe Ang, Dong Kyun Sohn, Liang Choo Hsia
  • Patent number: 7169675
    Abstract: A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: January 30, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Chung Foong Tan, Jinping Liu, Hyeokjae Lee, Kheng Chok Tee, Elgin Quek
  • Patent number: 7134966
    Abstract: A golf putt training device which is characterized as follows. A light apparatus adapted to project an alignment segment and an aiming spot on a playing surface. Whereby the light apparatus is positioned behind a ball and the aiming spot is projected in front of the ball. The alignment segment is projected over the ball and a putter head. The alignment segment is used to align the putter head during a swing. The method for putt training can begin by projecting an alignment segment and an aiming spot from a light apparatus positioned above a playing surface onto a playing surface. A ball is positioned on a portion of the alignment segment on the playing surface. A putter head of a putter is placed behind the ball on a portion of the alignment segment. The putter head is aligned with the alignment segment. The putter head is moved to strike the ball using the alignment segment to maintain the alignment of the putter head with the alignment segment.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 14, 2006
    Inventor: Robert M. Tice
  • Patent number: 7101743
    Abstract: A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: September 5, 2006
    Assignee: Chartered Semiconductor Manufacturing L.T.D.
    Inventors: Yisuo Li, Francis Benistant, Kian Meng Tee, King Jien Chui
  • Patent number: 7094669
    Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: August 22, 2006
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Xiaomei Bu, Alex See, Tae Jong Lee, Fan Zhang, Yeon Kheng Lim, Liang Choo Hsia
  • Patent number: 7089522
    Abstract: A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: August 8, 2006
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Patrick Tan, Kheng Chok Tee, David Vigar, Tat Wei Chua
  • Patent number: 7084025
    Abstract: A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: August 1, 2006
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Timothy Wee Hong Phua, Kheng Chok Tee, Liang Choo Hsia
  • Patent number: 7071069
    Abstract: A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 4, 2006
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Chung Foong Tan, Hyeokjae Lee, Eng Fong Chor, Elgin Quek
  • Patent number: 7069533
    Abstract: A system, apparatus and method for changing/modifying a customer specific reticle set design to a reticle set design that meets a user's process standard. An example embodiment of a method of modifying layout information representing a reticle set design for an integrated circuit comprising the following: receiving layout information and job information; and storing the layout information and the job information; the layout information representing a reticle set design for an integrated circuit and the job information related to the reticle set design; modifying the layout information and the job information to put the layout information and the job information into a first process compatible format; using the layout information and the job information to create mask writer format information for the reticle set design; and storing the mask writer format information; and outputting the mask writer format information.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: June 27, 2006
    Assignee: Chatered Semiconductor Manufacturing, LTD
    Inventors: Danchai Kochpatcharin, Jennifer Teong Su Ping, Yee Hwee Phuan, Elizabeth Lim, Kenneth Ngeow Zoo Khean, Winson Yong
  • Patent number: 7064358
    Abstract: An embodiment is a Electro Static Discharge (ESD) protection device comprising: a n-doped region and a p-doped region in a p-well in a semiconductor structure. The n-doped region and the p-doped region are spaced. A n-well and a deep n-well surrounding the p-well on the sides and bottom. A first I/O pad connected to the n-doped region. A trigger circuit connected the first I/O pad and the p-doped region. A second I/O pad connected to the n-well. A parasitic bipolar transistor is comprised of the n-doped region that functions as a collector terminal, the P-well that functions as a base terminal, and the deep N-well that functions as the emitter terminal. Whereby under an ESD condition, the p-well is charged positive using the trigger circuit and the parasitic bipolar transistor can be turned on.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: June 20, 2006
    Assignee: Chartered SemiConductor Manufacturing, LTD
    Inventors: Indrajlt Manna, Keng Foo Lo, Pee Ya Tan, Raymond Filippi
  • Patent number: 7052372
    Abstract: A polish apparatus for planarizing wafers and films over wafers comprising the following. A substrate chuck for holding a substrate with a surface to be polished thereof being directed about vertically. A first drive means for rotating the substrate chuck. A polishing head having a polishing surface which is adjacent to the substrate during the polishing of the substrate. The polishing surface of the polishing head is smaller than the surface of the substrate. A polishing solution supply means for supplying a polishing solution through the polishing head to the substrate held by the substrate chuck. A reciprocating means for reciprocally moving the polishing head on the surface to be polished. A pressing means for pressing the polishing pad against a substrate held by the substrate chuck by way of the polishing head. The polish head is preferably comprised of one piece of molded polymer. No polish pad is used.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: May 30, 2006
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Seng-Keong Victor Lim, Paul Richard Proctor, Robert Chin Fu Tsai