Abstract: A method of manufacturing a charge storage layer for a SONOS memory device. A feature of the embodiment is the first gate layer is formed over the charge storing layer (ONO) before the charge storing layer is patterned. The first gate layer protects the charge storing layer (ONO) from various etches used in the process to pattern the various gate dielectric layers on other regions of substrate.

Abstract: A structure, a method of fabricating and a method of using a phase shift mask (PSM) having a first phase shifted section, a half tone section, and a second phase shifted section. The first phase shift section and the half tone section are shifted 180 degrees with the second phase shift region. Embodiments provide for (1) a half tone, single trench alternating phase shift mask and (2) a half tone, dual trench alternating phase shift mask. The half tone region provides advantages over conventional alternating phase shift masks.

Abstract: A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer.

Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.

Abstract: An exercise device for simulating jump roping and for providing a total body workout that is held and rotated in use, comprised of two units; each unit to be held in a hand of a user. The units each comprised of (1) a handle, (2) an elongated first element attached to the handle, and (3) the elongated element has at least a first loop. The units preferably include a loop forming device for forming a loop from a portion of the elongated first element. The loop forming device can be located inside or outside the handle. The units can include additional elongated elements or loops. In other preferred embodiments, the exercise units are comprised of: a handle, and an elongated first element attached to the handle, and the elongated element providing weight and air resistance during the rotation of the elongated first element.

Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.

Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.

Abstract: A method for forming an antifuse interconnect structure, for a one-time fusible link, with field-programmable gate arrays, has been developed. The process features the use of an amorphous silicon layer, used as the antifuse layer, with the sidewalls of the amorphous silicon layer protected by critical silicon nitride sidewall spacers, during the patterning/etch procedure of the overlying metal layer. The protective sidewall spacers prevent the amorphous Si antifuse from being etched by subsequent processes.

Abstract: A plasma etch process for organic low-k dielectric layers using NH3 only, or NH3/H2 or NH3/H2 gases. A low k dielectric layer is formed over a substrate. A masking pattern is formed over the low k dielectric layer. The masking pattern has an opening. Using the invention's etch process, the low k dielectric layer is etched through the opening using the masking pattern as an etch mask. In a first embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3 gas. In a second embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/H2 gas. In a third embodiment, the etch process comprises: etching the low k dielectric layer by applying a plasma power and flowing only NH3/N2 gas. The invention's NH3 containing plasma etch etches organic Low k materials unexpectedly fast.

Abstract: An embodiment for a method for forming a self-passivated copper interconnect structure. An insulating layer is formed over a semiconductor structure. An opening is formed in the insulating layer. Next, we form a fill layer comprised of Cu and Ti over insulating layer. In a nitridation step, we nitridize the fill layer to form a self-passivation layer comprised of titanium nitride over the fill layer.

Abstract: A method with three embodiments of manufacturing metal lines and solder bumps using electroless deposition techniques. The first embodiment uses a PdSix seed layer 50 for electroless deposition. The PdSix layer 50 does not require activation. A metal line is formed on a barrier layer 20 and an adhesion layer 30. A Palladium silicide seed layer 50 is then formed and patterned. Ni, Pd or Cu is electroless deposited over the Palladium silicide layer 50 to form a metal line. The second embodiment selectively electrolessly deposits metal 140 over an Adhesion layer 130 composed of Poly Si, Al, or Ti. A photoresist pattern 132 is formed over the adhesion layer. A metal layer 140 of Cu or Ni is electrolessly deposited over the adhesion layer. The photoresist layer 132 is removed and the exposed portion of the adhesion layer 130 and the underlying barrier metal layer 120 are etched thereby forming a metal line.

Abstract: A method and structure for a device with a signal line over a semiconductor structure where the signal line is formed over the ground plane, passivation layer, and polyimide layer. We provide a semiconductor structure comprising a substrate having devices formed thereover and a plurality of insulating and conductive layers thereover. Next, we form ground plane over the semiconductor structure. The ground plane is the top metal layer over an inter metal dielectric layer. We then form a passivation layer over the ground plane. We form a first dielectric (e.g., polyimide) layer over the passivation layer. Subsequently, we form a signal line over the first dielectric layer. The signal line is formed by a plating or printing. We form a second dielectric layer (e.g., polyimide over the signal line and the first dielectric layer.

Abstract: A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

Abstract: A method and a structure for a parasitic bipolar silicided ESD device that has high resistivity regions within the collector of the parasitic NPN. The device has the structure of a N-MOS transistor and a substrate contact. The device preferably has silicide regions over the doped regions. The invention has two types of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) undoped or lightly doped regions (e.g., channel regions). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n−well (n minus well) can be formed under the collector. The high resistivity regions increase the collector resistivity thereby improving the performance of the parasitic bipolar ESD device.

Abstract: A method and an integrated circuit having power rails under transistors. In a preferred embodiment, power rails are formed over a substrate. Devices, such as FET transistors, are formed over the power rails. A preferred device is an inverter. The method comprises forming a first power rail (VSS) over the substrate. Then forming a second power rail (e.g., VDD) over the first power rail. The second power rail is insulated from the first power rail. Next, transistors are formed over the first and the second power rails.

Abstract: A structure and a method for a stitched write head having a sunken share pole. The method includes forming a bottom coil dielectric layer over the first half shared pole. Coils are formed over the bottom coil dielectric layer. Next, second half shared poles (P1) are formed over the first half shared pole (S2). We form a top coil dielectric layer over the structure. In a key step, we chemical-mechanical polish the top coil dielectric layer. A write gap layer (WG) is formed over the front second half shared pole and the top coil dielectric layer over the coils. An upper pole (P3) and hard mask are formed over the write gap layer. We etch the write gap layer and the second half shared pole (P1) using the upper pole as an etch mask to remove a portion of the second half shared pole (P1) adjacent to the write gap layer thereby forming a partially trimmed pole.

Abstract: A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions.

Abstract: The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

Abstract: A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p+ diffusion region. The emitter and the substrate act as a first diode D1 and the collector and the substrate act as a second diode D2. The second embodiment has a first N+ well between a second n+ (collector) region and a P+ base region. The Vt1 is controlled by the dopant profiles of the P+ base and the n− first well where they intersect. The third embodiment is similar to the second embodiment, but the n− well covers all of drain. A parasitic NPN bipolar transistor comprises: an emitter, a parasitic base and a drain. The emitter is formed by the first n+ region. The parasitic base is formed by the p-substrate.

Abstract: A structure for preventing and controlling Arcing Across Thin Dielectric Film in sputtering and other process that generate electric fields and cause arcing across conductive structures. In an embodiment, an extraneous window or two extraneous windows are formed in a second dielectric layer under at least of a portion of a lead to that a “hot spot” area is created where arcing is more likely to occur.