Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract: The present invention provides a method of manufacturing a nickel-silicide technology for polysilicon interconnects. Nickel 40 is deposited on polysilicon 30 using a electroless process. Using a rapid thermal anneal process, Ni 40 is transformed to NiSi at about 600° C. without any agglomeration. The method comprises forming a polysilicon layer 30 over a substrate 10. The surface 34 of the polysilicon layer is activated. Nickel 40 is selectively electroless deposited onto the surface of the polysilicon layer forming a Nickel layer over the polysilicon layer. The Ni layer 40 is rapidly thermally annealed forming a Nickel silicide layer 36 over the polysilicon layer 30. The rapid thermal anneal is performed at a temperature of about 600° C. for a time of about 40 sec. The Nickel silicide layer 36 preferably comprises NiSi 36B with a low resistivity.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

Abstract: A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer layers.

Abstract: A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug.

Abstract: An improved MOS transistor and method of making an improved MOS transistor. An MOS transistor having a recessed source drain on a trench sidewall with a replacement gate technique. Holes are formed in the shallow trench isolations, which exposes sidewall of the substrate in the active area. Sidewalls of the substrate are doped in the active area where holes are. Conductive material is then formed in the holes and the conductive material becomes the source and drain regions. The etch stop layer is then removed exposing sidewalls of the conductive material, and oxidizing exposed sidewalls of the conductive material is preformed. Spacers are formed on top of the pad oxide and on the sidewalls of the oxidized portions of the conductive material. The pad oxide layer is removed from the structure but not from under the spacers. A gate dielectric layer is formed on the substrate in the active area between the spacers; and a gate electrode is formed on said gate dielectric layer.

Abstract: A method for forming a binary intensity mask (BIM) using two writing steps. The first writing step has a narrow writing area, preferably about 1 micron, and outlines the desired pattern. The second writing area partially overlaps the first writing area, preferably by less than half of the E-beam diameter used for writing. The second writing does not overlap the desired pattern. The chromium layer of the BIM is dry etched after the first writing, providing good edge definition and dimensional stability. The chromium layer of the BIM is wet etched following the second writing reducing mask defects.

Abstract: A method for forming a wide gate stack over a gate in a rf device is described. The invention reduces the gate resistance and the Rs significantly. A substrate has a digital area and a rf area. Devices used in digital circuits will be formed in the digital area and devices used in RF circuits will be formed in the rf area. In both rf and digital areas, gate structure are provided comprising: a gate dielectric and a gate electrode, Source and drain (S/D) regions, source and drain silicide regions, gate silicide regions over the gate electrode. We form a stop layer over the substrate. Next, we form a first interlevel dielectric layer over the stop layer. We polish the first interlevel dielectric layer and the stop layer to expose the gate silicide region. Next, we form a polish stop layer and a second interlevel dielectric layer over the surface. In the digital area, we form a contact holes and in the rf area we to expose the source and drain silicide regions.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer is formed on the substrate structure. Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer is formed over the silicon oxynitride layer and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm 250 nm, the silicon oxynitride layer provides a phase-cancel effect.

Abstract: A method for repairing shifter layer defects in a phase shifting mask. A two step process is used to form an equivalent shifter layer with about the same light transmittance and phase angle shift as an original, non-defective shifter layer. (Typically for a DUV APSM, transmittance is about 6% and phase angle shift is about 180 degrees.) The first step is to etch the quartz substrate in a focus ion beam repair machine, using XeF2 gas, to cause a leading phase angle shift. The second step is to deposit an equivalent shifter layer in-situ in the focus ion beam repair machine, using a carbon based gas. When the equivalent shifter layer has about the same transmittance as the original shifter layer (e.g. 6%), the phase angle is lagging less than 180 degrees. The leading phase angle shift caused by etching the quartz substrate and the lagging phase angle caused by the equivalent shifter layer combine to produce a phase angle 180 degrees leading.

Abstract: The present invention provides a boat and method for holding one or more substrates during a ball grid array packaging assembly. The boat comprises a base and one or more spring locks. The base has one or more openings which provide access to both faces of said substrates. The base has bottom supports protruding into the openings to retain the substrates from below and top supports protruding into the openings to retain the substrates from above. The spring locks apply lateral pressure to the substrates forcing the substrates over the bottom supports and under the top supports, whereby the boat can be flipped with the substrates retained between the top supports and the bottom supports. In one embodiment, substrates are installed in the boat, and the entire boat is flipped when the opposite face needs to be accessed, rather than manually flipping each substrate.

Abstract: The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

Abstract: The present invention provides a method for forming and etching a resist protect oxide layer, of which provides improved etch selectivity to a shallow trench isolation and an increased pre-metal dip processing window. The process begins by forming a shallow trench isolation on a semiconductor substrate. The semiconductor substrate has a first area and a second area separated by the shallow trench isolation. A gate is formed on the semiconductor substrate in the first area, adjacent to the shallow trench isolation. In a key step, a resist protect oxide layer comprising a thin silicon oxide layer and an overlying thin nitrogen containing layer, is deposited over the semiconductor substrate, the gate, and the shallow trench isolation. The thin nitrogen containing layer can be composed of silicon nitride or silicon oxynitride.

Abstract: A method for fabricating a junction for a field effect transistor which does not cause distortion of the sidewall spacers during subsequent processing thereby reducing junction depletion and source to drain leakage. The process begins by providing a substrate structure having a gate thereon. Sidewall spacers are formed on the sidewalls of the gate. Impurity ions are implanted into the substrate structure adjacent to the gate to form source and drain regions. A resist protect oxide layer is formed over the substrate structure. The resist protect oxide is patterned by forming a mask over the resist protect oxide layer having an opening over the gate and the source and drain regions. The resist protect oxide layer is selectively etched; thereby removing the resist protect oxide over the source and drain regions without distorting the sidewall spacers. A silicide region is formed on the source and drain regions using a salicide process comprising a pre-amorphous implant and one or more rapid thermal anneal steps.

Abstract: The present invention provides an anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer and two compatible oxide etch processes. The Si-Rich Silicon oxynitride (SiON) etch barrier layer can be used as a hard mask in a dual damascene structure and as a hard mask for over a polysilicone gate. The invention has the following key elements: 1) Si rich Silicon oxynitride (SiON) ARC layer, 2) Special Silicon oxide Etch process that has a high selectivity of Si-Rich SiON to silicon oxide or SiN; 3) Special Si Rich SiON spacer process for a self aligned contact (SAC). A dual damascene structure is formed by depositing a first dielectric layer. A novel anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer is deposited on top of the first dielectric layer. A first opening is etched in the first insulating layer. A second dielectric layer is deposited on the anti-reflective Si-Rich Silicon oxynitride (SiON) etch barrier layer.

Abstract: The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said substrate through said isolation opening to form a Si damaged or doped first region. The first region is selectively etching to form a hole. The hole is filled with an insulating material to form a balloon shaped shallow trench isolation (STI) region. The substrate has active areas between said balloon shaped shallow trench isolation (STI) regions. The second embodiment differs from the first embodiment by forming a trench in the substrate before the implant. The third embodiment forms a liner in the trench before an isotropic etch of the substrate through the trench.

Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.

Abstract: A method for forming a damascene structure over tungsten plugs using nitridation of said tungsten plugs to provide better oxidation resistance, better adhesion properties and better copper diffusion barrier proerties. The process begins by providing a substrate structure having at least one device layer thereon and having a first dielectric layer overlying the device layer. The dielectric layer has tungsten plugs therein providing a conductive path between the surface of the dielectric layer and the device layer. The tungsten plugs are nitriduzed to form a WNx layer on top of the tungsten plugs. A second dielectric layer is deposited over the WNx layer and the first dielectric layer. The second dielectric layer is patterned to form a trench in the second dielectric layer; whereby the WNx layer is exposed in the trench. A barrier layer is formed in the trench. A metal layer is formed over the barrier layer. The metal layer and the second dielectric layer are planarized to form a damascene structure.

Abstract: A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.