Patents Represented by Attorney William N. Hogg
  • Patent number: 7240430
    Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
  • Patent number: 7235148
    Abstract: A printed wiring board is formed from two or more layers, one of which has circuit lines formed thereon, and wherein the surfaces of the circuit lines are roughened only in areas that require good copper to laminate adhesion. The remainder of the circuit line surfaces are smooth. Thus, those areas for propagation of the signal on signal lines have the circuit lines smooth to maximize the signal propagation effect, while those areas where the signal propagation is not critical are rough, which improves the adhesion of one layer to another. On the voltage planes, the surface in those regions opposite the smooth surfaces of the signal planes is smooth. Thus, these areas of the voltage planes can be maintained smooth while the other areas of the surface of the voltage planes can be roughened, providing good adhesion to the adjoining dielectric material.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Richard Allen Day, Kevin Taylor Knadle, Kristen Ann Stauffer
  • Patent number: 7200696
    Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean Louis Calvignac, Marco C. Heddes, Joseph Franklin Logan, Fabrice Jean Verplanken
  • Patent number: 7091424
    Abstract: A coaxial via structure is adapted to transmit high speed signals or high intensity current through conductive layers of an electronic device carrier. The coaxial via structure comprises a central conductive track and an external conductive track separated by a dielectric material and is positioned in a core of the electronic device carrier or in the full thickness of the electronic device. The coaxial via structure can be combined with a stacked via structure so as allow efficient transmission of high speed signals across the electronic device carrier when a manufacturing process limits the creation of a full coaxial via structure across the entire electronic device carrier.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: August 15, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stefano S. Oggioni, Gianluca Rogiani, Mauro Spreafico, Giorgio Viero
  • Patent number: 7078802
    Abstract: A method and resulting electronic package in which a heat sink is secured to the package's dielectric material (e.g., overmold). The surface of the dielectric is roughened (e.g., using an abrasive paper or pad) to enhance the subsequent dielectric-heat sink bond in which an adhesive is used. The dielectric material's roughened external surface(s), typically containing silicone material (e.g., silicone residue) which is an inherent by-product of many dielectric materials of the type used in such packaging, is (are) able to still be securely attached to the heat sink, despite the presence of said silicone. In another embodiment, the roughened surface enhances the marking of dielectric material of this type (e.g., using ink).
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Gaynes, William R. Hill
  • Patent number: 7059060
    Abstract: A device for recording both chronological events and physical growth events of an individual or group of individuals' lives. The device includes linear measuring device having at least first and second opposed sides. The first side has a linear measurement scale inscribed thereon and at least one recording surface associated therewith. The second side has a chronological scale, preferably in months and years, inscribed thereon and also has at least one recording surface associated with the chronological scale. Thus, physical growth can be measured on the first side and recorded on the recording surface associated therewith as the individual or several individuals grow physically. Significant events can be recorded on the other side.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: June 13, 2006
    Inventor: Daryl L. Baumgartner
  • Patent number: 7045562
    Abstract: A method of self-healing cracks in a cured epoxy base underfill material between an I/C chip and a substrate is provided. A plurality of capsules is dispersed in the epoxy base. Each capsule has a curable thermosetting adhesive encapsulated in a rupturable shell to disperse the thermosetting adhesive in a crack in the epoxy base when the shell ruptures. Each capsule is less than 25 microns in diameter. A curing agent that will cause a reaction of the thermosetting adhesive on contact is dispersed in the epoxy to form a cured adhesive in a crack in said epoxy base. The shell will rupture when encountering a crack being propagated in the underfill material, which will at least partially fill the crack with the adhesive, and cure the adhesive with the curing agent to bond the edges of the crack together. The invention also includes the structure for crack self-healing.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: May 16, 2006
    Assignee: International Business Machines Corporation
    Inventor: George H. Thiel
  • Patent number: 7038469
    Abstract: A method of determining electron tunneling values at various locations in a capacitor structure having a first and a second conductive plate with a dielectric material disposed there between, wherein each plate has first and second ends, including the steps of: determining the nominal tunneling voltage of the dielectric material at its thickness to provide a target voltage. Applying a first voltage level equally across the first plate. Applying a second voltage level to the first end of the second plate which together with the voltage applied to the first plate establishes a positive offset voltage with respect to the target voltage. Applying incrementally changing voltage levels to the second end of the second plate, which varying voltage levels change the voltage at the second end of the second plate of each set to vary the length of the capacitive structure above the target voltage.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventor: Peter T. Coutu
  • Patent number: 7037819
    Abstract: A circuitized substrate and a method of making the circuitized substrate are provided. The circuitized substrate includes a substrate having a conductive pad thereon. A first layer of solder enhancing material is positioned on the conductive pad, the first layer of solder enhancing material includes a first region and a second region positioned relative to the first region. A solder member is positioned on the first region of the first layer of solder enhancing material. A second layer of solder enhancing material is positioned on the solder member and on a portion of the second region of the first layer of solder enhancing material. The circuitized substrate may be used in the fabrication of an electronic package.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Timothy A. Gosselin, Donald I. Mead
  • Patent number: 7024574
    Abstract: Electric apparatus, computer apparatus, controller, and battery switching method and program is provided to prevent a system shutdown caused by a reduction of electric power from a battery. A computer apparatus is constructed to be able to accept and be powered by a rechargeable main battery and a rechargeable sub-battery. An embedded controller in the computer apparatus monitors a remaining capacity at a pre-specified temperature of the sub-battery under discharge by receiving information from CPU. When the monitored temperature exceeds a predetermined temperature and when the monitored remaining capacity becomes less than a predetermined capacity, the embedded controller receives electric power from the main battery by switching the power supply circuit to provide power from the main battery instead of the sub-battery.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: April 4, 2006
    Assignee: Lenovo (Singapore) PTE LTD
    Inventors: Shigefumi Odaohhara, Akiyoshi Tanaka
  • Patent number: 7002181
    Abstract: Disclosed are a thin film transistor capable of controlling gray level of an organic LED element by discretely controlling current levels, a method of manufacturing the thin film transistor, an array substrate including the thin film transistor, a display device, and a method of driving the display device. The thin film transistor includes an active layer formed on an insulating substrate, a plurality of insulating layers formed oppositely to each other with the active layer interposed therebetween, a first gate electrode and a second gate electrode formed adjacently to the insulating layers, respectively, and wiring connected to the first and second gate electrodes, respectively, the wiring controlling respective potentials of the first and second gate electrodes independently of each other. The area of the first gate electrode is different from the area of the second gate electrode, and current levels can be discretely controlled in at least four levels.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: February 21, 2006
    Assignee: Toppoly Optoelectronics Corporation
    Inventors: Hiroshi Suzuki, Takatoshi Tsujimura
  • Patent number: 7001827
    Abstract: There is provided a method for making a wafer including the steps of providing a substrate having a first surface, an opposite second surface, and at least one side edge defining a thickness of the substrate, the at least one side edge having a first peripheral region and a second peripheral region adjacent to the first peripheral region. The method includes applying a fluid to the first surface and the first peripheral region of the at least one side edge and removing the opposite second surface and the second peripheral region of the at least one side edge to form a third surface. A semiconductor chip made from the method for making the wafer is also provided.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Allan D. Abrams, Donald W. Brouillette, Joseph D. Danaher, Timothy C. Krywanczyk, Rene A. Lamothe, Ivan J. Stone, Matthew R. Whalen
  • Patent number: 6995475
    Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith, Randolph F. Knarr, Sarah H. Knickerbocker, Kevin S. Petrarca, Roger A. Quon, Wolfgang Sauter, Kamalesh K. Srivastava, Richard P. Volant
  • Patent number: 6988882
    Abstract: A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting the first and second cavities. The first cavity is adapted to enclose the integrated circuit chip on the substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: January 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Marie-France Boyaud, Catherine Dufort, Marie-Claude Paquet, Real Tetreault
  • Patent number: 6986198
    Abstract: A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Patent number: 6985362
    Abstract: A printed circuit board on which a semiconductor chip is flip chip mounted, comprising a circuit pattern to which a conductive bump, provided in a corner portion of a semiconductor chip, is connected, an insulating layer for holding the circuit pattern, and a protection pad which is positioned on the insulating layer relative to the circuit pattern, to which the conductive bump is connected.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Hiroyuki Mori, Yutaka Tsukada, Kimihiro Yamanaka
  • Patent number: 6967389
    Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: William Infantolino, Voya R. Markovich, Sanjeev B. Sathe, George H. Thiel
  • Patent number: 6963868
    Abstract: A tree structure and method to organize routing information for processing messages within a network, each message being associated with a search key of “n” bits. The processing determines where to send the message next. The structure has a direct table (DT) of 2x entries for decoding the first “x” bits of the search key, and one or more pattern search control blocks (PSCB's), each having 2m entries for decoding subsequent groups of “m” bits. Each PSCB entry and DT entry includes a pointer to data associated with a specific route, if at this point a specific routing table entry is a potential match to the search key or a pointer to a subsequent PSCB if the end of a search trail is not identified. Each PSCB entry DT entry also indicates that the search has been resolved to the end of the search trail.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: November 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean L. Calvignac, Gordon T. Davis, Marco Heddes, Piyush C. Patel, Steven R. Perrin, Grayson W. Randall
  • Patent number: 6956296
    Abstract: A method, mold and apparatus for encapsulating and underfilling an integrated circuit chip assembly. The mold has a first portion and a second portion with the first portion having first and second cavities and at least one channel interconnecting said first and second cavities. The first cavity is adapted to enclose said integrated circuit chip on said substrate. A clamping force is applied to the first and second portions of the mold to clamp the substrate between them with the integrated circuit chip located in the first cavity. Vents exhaust air from the first cavity. Encapsulant is injected into the first cavity of the first portion at a location in the first portion remote from the point of connection of the channel such that encapsulant flows around and underneath the integrated circuit chip and through the channel into the second cavity to thereby underfill and encapsulate the integrated circuit assembly.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: October 18, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marie-France Boyaud, Catherine Dufort, Marie-Claude Paquet, Real Tetreault
  • Patent number: 6932617
    Abstract: A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Pierre Debord, Rene Glaise, Claude Gomez