Abstract: Disclosed are a thin film transistor capable of controlling gray level of an organic LED element by discretely controlling current levels, a method of manufacturing the thin film transistor, an array substrate including the thin film transistor, a display device, and a method of driving the display device. The thin film transistor of the present invention includes an active layer formed on an insulating substrate, a plurality of insulating layers formed oppositely to each other with the active layer interposed therebetween, a first gate electrode and a second gate electrode formed adjacently to the insulating layers respectively, and wiring connected to the first and second gate electrodes respectively, the wiring controlling respective potentials of the first and second gate electrodes independently of each other. The area of the first gate electrode is different from the area of the second gate electrode, and current levels can be discretely controlled in at least four levels.

Abstract: A prepreg resin comprising: (a) 98 to 40% by weight based on the total weight of components (a) and (b), of a curable polyphenylene ether resin; (b) 2 to 60% by weight based on the total weight of components (a) and (b), of at least one cyanurate selected from the group consisting of triallyl isocyanurate and triallyl cyanurate; (c) a polymerization initiator comprised of a peroxide functionalized polymer, said peroxide functionalized polymer being fragmented by heat to a plurality of free radical moieties, such as t-butoxide moieties, and a relatively inert moiety having a molecular weight greater than about 1,000. The invention also encompasses a cured resin either as a coating on a substrate, without fiberglass cloth embedded, or a cured prepreg with fiberglass cloth embedded and a method of forming the same.

Abstract: An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal. The chip carrier further includes a reference structure having at least two conductive layers such that the signal track is electrically shielded by the reference structure. A semiconductor chip is positioned on the chip carrier and includes at least one terminal electrically interconnected to the at least one contact area.

Abstract: A multi-layered circuitized substrate for high-frequency applications. Conductive via-holes extend between two non-adjacent conductive layers for transmitting high-frequency signals therebetween. For each via-hole, shielding rings connectable to a reference voltage are provided, each ring formed in a corresponding intermediate conductive layer between the two non-adjacent conductive layers. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands at the ends thereof, in order to reduce stray capacitance associated with the via-hole without losing the shielding effect provided by the rings.

Abstract: A method of forming solder connections on a circuitized substrate having connection pads is provided. A laser ablatable solder mask material, preferably an epoxy, is degassed and then dispensed as a liquid onto the substrate over the circuitization. The surface of the solder mask material as applied is leveled, and the solder mask material is then cured to form a solder mask. Openings are laser ablated in the solder mask material to reveal those connection pads which are to receive solder to form the solder connections. Liquid solder is dispensed under pressure in a confined space into the openings as blades move laterally on top of the solder mask to fill the openings in the solder mask. The solder material is then solidified to form domed solder bumps in the openings.

Abstract: A method for fabricating circuitized substrates which reduces shorts, and does not require baking and resulting film. The method employs a photoimageable dielectric film, having a solvent content less than about 5%, and a glass transition temperature, when cured, which is greater than about 110° C. A photoimageable dielectric film, is provided having from about 95% to about 100% solids, and comprising: from 0% to about 30% of the solids, of a particulate rheology modifier, from about 70% to about 100% of the solids of an epoxy resin system (liquid at 20° C. comprising: from about 85% to about 99.9% epoxy resins; and from about 0.1 to 15 parts of the total resin weight, a cationic photoinitiator; from 0 to about 5% solvent, applying the photoimageable dielectric film to a circuitized substrate; and exposing the film to actinic radiation.

Abstract: An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.

Abstract: A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8.

Abstract: The present invention provides new methods for electroless plating of metal particularly gold and copper onto substrates, such as circuitized substrates, which reduces processing steps, reduces metal consumption, and reduces the scraping of parts due to contamination. The method employs a permanent plating resist. The method for electrolessly plating metal onto a substrate, including the following steps: providing: an uncured, photoimagable, dielectric permanent plating resist comprising: from about 10 to 80% of phenoxy polyol resin which is the condensation product of epichlorohydrin and bisphenol A, having a molecular weight of from about 40,000 to 130,000; from about 20 to 90% of an epoxidized multifunctional bisphenol A formaldehyde novolac resin having a molecular weight of from about 4,000 to 10,000; from 0 to 50% of a diglycidyl ether of bisphenol A having a molecular weight of from about 600 to 2,500; and from about 0.

Abstract: A platen for use in a laminating press is provided which includes a body of material having first and second faces and spaced first and second ends. Preferably, at least one heating device is disposed in the body of material. First and second spaced cooling channels are formed in the body of material, the first cooling channel being adjacent the first face and having a fluid inlet port adjacent to or in the first end, and a fluid outlet port adjacent to or in the second end, and a second cooling channel being adjacent the second face and having a fluid inlet port adjacent to or in said second end, and a fluid outlet port adjacent to or in the first end. The invention also contemplates using such platens for laminating a book or stack of sheets of material to form a unitary single member having reduced stresses.

Abstract: A method for manufacturing a circuit board having a conductive via comprises the steps of providing a substrate having a first surface and a first conductive layer on at least one region of the first surface, forming an insulating layer on the first conductive layer, forming an opening in the insulating layer, so that the opening extending to the first conductive layer, forming a second conductive layer inside the opening and at least on the insulating layer near the opening, applying a positive photoresist on the second conductive layer, exposing the positive photoresist, developing the exposed positive photoresist, and removing the positive photoresist on the second conductive layer, except a portion of the second conductive layer that is inside the opening, etching the second conductive layer, to expose a surface of the second conductive layer, removing the positive photoresist from inside the opening, and forming a third conductive layer inside the opening.

Abstract: A ball grid array module is provided. In particular, the ball grid array module includes a substrate with two layers of insulation positioned thereon. At least one cavity having a side wall and a bottom wall is positioned in the first and second layers of insulation. The ball grid array module is adapted for having a solder ball positioned on the bottom wall of the cavity. During heating and reflow of the solder ball, positioning of the solder ball in the cavity prevents dislodging of the solder ball.

Abstract: A structure and technique for forming an I/C chip module and circuit card construction is provided. An I/C chip module having a flexible substrate, with first and second opposite sides concave, results from the CTE mismatch between the I/C chip and substrate. The I/C chip module is mounted on a flexible circuit card by solderball connection. The curvature of the I/C chip module causes the circuit card to curve correspondingly. A heatsink in thermal contact with the I/C chip places pressure on the I/C chip module in a direction to decrease the curvature. A rigid backing member retains the circuit card, generating a curved space between the backing member and the circuit card. A leaf spring applies pressure to the I/C chip module against the backing member. A compliant member is interposed between the backing member and the circuit board filling a portion of the curved space therebetween.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: An apparatus for designing a printed wiring board comprises an input section for receiving information necessary to design the board, information on components to be mounted on the board, and information on connection between the components; a storage section for storing the information such as the board information, the component information, the connection information, and the information obtained form printed wiring boards designed in the past; a display section for displaying the input information and various information on designing; and a calculation/control section for performing predetermined calculations by the use of various information stored in the storage section and controlling the input section, the display section, and the storage section, wherein the ratio of a total wirable length to a total wiring length necessary to connect components is determined on the basis of various information stored in the section 38, and a PWB grade of the board is selected based on this ratio.

Abstract: A method of forming a member for joining to form a composite wiring board. The member includes a dielectric substrate. Adhesive tape is applied to at least one face of said substrate. At least one opening is formed through the substrate extending from one face to the other and through each adhesive tape. An electrically conductive material is dispensed in each of the openings and partially cured. The adhesive tape is removed to allow a nub of the conductive material to extend above the substrate face to form a wiring structure with other elements.

Abstract: A technique for making acicular, branched, conductive dendrites, and a technique for using the dendrites to form a conductive compressible pad-on-pad connector are provided. To form the dendrites, a substrate is provided on which dendrites are grown, preferably on a metal film. The dendrites are then removed from the substrate, preferably by etching metal from the substrate. The so formed dendrites are incorporated into a compressible dielectric material, which then forms a compressible pad-on-pad connector between two conducting elements, such as connector pads on electrical devices, e.g. an I/C chip mounted on a substrate, such as a chip carrier.

Abstract: The electrical properties of the bond formed between a metal substrate and an electrically conductive adhesive is improved, especially in high humidity conditions, by applying to the metal substrate an organic coupling agent prior to application of the electrically-conductive adhesive thereto.

Abstract: A printed wiring board is formed from two or more layers, one of which has circuit lines formed thereon, and wherein the surfaces of the circuit lines are roughened only in areas that require good copper to laminate adhesion. The remainder of the circuit line surfaces are smooth. Thus, those areas for propagation of the signal on signal lines have the circuit lines smooth to maximize the signal propagation effect, while those areas where the signal propagation is not critical are rough, which improves the adhesion of one layer to another. On the voltage planes, the surface in those regions opposite the smooth surfaces of the signal planes is smooth. Thus, these areas of the voltage planes can be maintained smooth while the other areas of the surface of the voltage planes can be roughened, providing good adhesion to the adjoining dielectric material.

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.