Abstract: An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.

Abstract: A method of disposing of a rocket motor 12 comprises burning propellant contained within the motor and generating an enclosure 13 of liquid within which the burning occurs. Apparatus for carrying out the method comprises a nozzle/clamping unit 1 for securing the rocket motor 12 in place and generating the liquid enclosure 13. The liquid, which may be water and may include neutralising chemicals, is filtered and recycled.

Abstract: A memory module for attachment to a computer system having a memory bus and a method of using the memory module for error correction by scrubbing soft errors on-board the module is provided. The module includes a printed circuit card with memory storage chips on the card to store data bits and associated ECC check bits. Tabs are provided on the circuit card to couple the card to the memory bus of the computer system. Logic circuitry selectively operatively connects and disconnects the memory chip and the memory bus. A signal processor is connected in circuit relationship with the memory chips.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: A method of forming an isotropic electrical connection and a mechanical bond between two articles having metal surfaces thereon and the resulting bond is provided. Preferably, the metal surfaces are the surfaces of metal contact pads on a dielectric substrate and on an electronic device such as an I/C chip or chip carrier. The mechanical bond and electrical connection is provided by utilizing a conductive adhesive, in which adhesive the conduction is provided by metal particles which have exposed palladium thereon. The particles may be the metal palladium itself or it may be some other metal, such as silver, having palladium coated thereon, preferably by electrodeposition. The particles typically are flakes with the palladium having an incipient dendritic form on the surface, i.e.; the palladium has a multi-pointed surface configuration that can grow into fully formed needle-like dendritic structures. However, the shape of the particle is not significant.

Abstract: An improved memory module and its use in a computer system is provided. The module includes a DSP first and second individually addressable banks of memory chips. The first bank is configured to function principally under the control of the signal processing element and the second bank is configured to function principally under the control of a system memory controller, although all the portions of each of the memory banks is addressable by both the signal processing element and the system memory controller. Both banks of memory chips can be placed in at least one higher power state and at least one lower power state by either the system memory controller or the DSP. The activity of each bank is sensed while in the higher power state, and the condition of each of the banks is sensed with respect to any activity during operation of the memory bank at the higher power state.

Abstract: A technique for making acicular, branched, conductive dendrites, and a technique for using the dendrites to form a conductive compressible pad-on-pad connector are provided. To form the dendrites, a substrate is provided on which dendrites are grown, preferably on a metal film. The dendrites are then removed from the substrate, preferably by etching metal from the substrate. The so formed dendrites are incorporated into a compressible dielectric material, which then forms a compressible pad-on-pad connector between two conducting elements, such as connector pads on electrical devices, e.g. an I/C chip mounted on a substrate, such as a chip carrier.

Abstract: An explosion-suppressing structure comprises an explosion-suppressing barrier, such as a wall of liquid-filled tanks or blocks, and rupturable explosion-suppressing roof members 23 such as hollow rigid bodies containing liquid-filled bags 24 and supporting further bags 25. In an alternative embodiment, the roof member comprises a net stretched over the barrier.

Abstract: A method and device for attaching a module having a ball grid array or column grid array of solder material thereon arranged in a given pattern or footprint to a substrate having an array of connector pads arranged in the same pattern is provided. A preformed alignment device has an array of through holes therein aligned in the same pattern or footprint as the ball grid array or column pattern on the module and the pattern of contact pads on the substrate. The through holes in the preform are filled with a solder material which can be either a solder paste or a solid solder or with a curable conductive adhesive. The solder preferably is a lead-tin eutectic, but in any event has a melting point of less than about 240° C. and in the case of the conduction adhesive, will cure below about 240° C. The preform with the filled through holes is interposed between the module and the substrate with the material in the holes in contact with the solder balls or columns and the contact pads.

Abstract: A method for attaching adherent metal components, particularly a copper film, on at least one surface of a polyimide substrate is provided. The method comprises the steps of: exposing at least one surface of the polyimide substrate to a reactive gas plasma that provides a level of ion bombardment of the polyimide surface sufficient to disrupt at least a portion of the imide groups on the surface and to form reactive carboxylate groups, carbonyl groups and other carbon-oxygen functional groups on the surface; and then depositing a metal film onto the chemically-modified surface without intervening exposure to air. The present invention also provides a copper-coated polyimide product comprising a polyimide substrate having a substantially smooth and chemically-modified surface and a copper film directly attached to the surface, i.e., the product is free of a polymeric adhesive layer or tie coat between the surface of the polyimide substrate and the copper film.

Abstract: A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Abstract: An apparatus for simultaneously testing or burning in a large number of the integrated circuit chips on a product wafer includes probes mounted on a first board and tester chips mounted on a second board, there being electrical connectors connecting the two boards. The tester chips are for distributing power to the product chips or for testing the product chips. The probes and thin film wiring to which they are attached are personalized for the pad footprint of the particular wafer being probed. The base of the first board and the second board both remain the same for all wafers in a product family. The use of two boards provides that the tester chip is kept at a substantially lower temperature than the product chips during burning to extend the lifetime of tester chips. A gap can be used as thermal insulation between the boards, and the gap sealed and evacuated for further thermal insulation.

Abstract: A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline.

Abstract: It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material.

Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.

Abstract: An electronic package wherein an electronic device (e.g., chip) on a circuitized substrate of the package is thermally coupled to a heatsink in a separable manner using a plurality of compressible, thermally conductive members (e.g., solder balls). These members are compressed and permanently deformed as part of the thermal coupling.

Abstract: A serial bus and connection to a device on a computer system through a system memory controller is provided on a memory card having a DSP and a memory bus controller to allow the DSP on the memory card to gain access to the system device without using the system memory bus. The serial bus is a two wire serial bus connecting the device to the DSP through the system memory controller. If more than one memory card is present with DSPs or more than one device is contending for access, the system memory controller or arbitrate the access of each memory card or contending device. In such case the serial bus will signal the system memory controller when it wants access to the particular device, and the system memory controller will act as arbitrator to grant or not grant access to the particular memory card or device requesting access. If access is granted the bus memory controller outputs the required control or command word on the serial bus followed by the address and the required data.