Patents Represented by Attorney William T. Ellis
  • Patent number: 4957875
    Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: September 18, 1990
    Assignee: International Business Machines Corporation
    Inventors: Shah Akbar, Patricia L. Kroesen, Seiki Ogura, Nivo Rovedo
  • Patent number: 4897154
    Abstract: A post dry etching process for restoring wafers damaged by dry etching such as RIE, comprising the steps of removing any dry etch residue layer from the etched portions of the wafer and forming an oxide on those etched portions; rapid thermal annealing the wafer to drive the oxygen from the oxide layer down into the wafer by a small amount, to getter impurities to this oxide layer, and to restore crystallinity below the oxide layer; and removing the oxide layer via an HF bath or a low powder dry etch process.
    Type: Grant
    Filed: July 3, 1986
    Date of Patent: January 30, 1990
    Assignee: International Business Machines Corporation
    Inventors: Satya N. Chakravarti, Stephen J. Fonash, Xiao-Chun Mu
  • Patent number: 4856000
    Abstract: Duplicated circuit arrangement comprising a main processor (30) and its P bit data bus (44), and two identical redundant devices (21:22), each device is comprised of a processing element (23;35) performing the same task in parallel on a P bits word, and send/receive circuits (24,25;36,37) controlled by the main processor through lines (SR11 to SR22) to transmit said word to and from said main processor. For each device, the send/receive circuits are split into two parts. Send/receive circuit of the first device (21) is split in two parts (24, 25); the first part (24) handles the P/2 Most Significant Bits (MSB's) and the second part (25) handles the P/2 Less Significant Bits (LSB's). In normal operation, during the transmission step, only the first part (24) is allowed to send bits on one half (33) of the data bus (44).
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: August 8, 1989
    Assignee: International Business Machines Corporation
    Inventors: Michel Bauge, Gerard Boudon, Pierre Mollier, Jean-Luc Peter, Yiannis J. Yamour
  • Patent number: 4852096
    Abstract: A CN.sup.2 memory testing circuit for generating a sequence of C(N.sup.2 +1) memory addresses which will accomplish a CN.sup.2 test with the least possible memory transitions. In one embodiment for an odd integer C, the mth bit in the memory address sequence comprises at least one repetition of a unique transition bit (UTB) pattern, where the UTB pattern comprisesUTB Pattern=(C+1)/2 entries of 00, concatenated with C-1 entries of 10, concatenated with (C+1)/2 entries of 11, to yield the transitions 0-0, 0-1, 1-0, and 1-1. The m+1th bit in this memory address sequence comprisesm+1th bit pattern=a plurality of different combinations of 00, 01, 10, and 11, in any order, but with each of the different bit combinations aligned, at least once, with each different transition in the UTB pattern.A second embodiment, with an even integer C, is similar to the first embodiment, but with a UTB pattern comprisingUTB pattern=C(2).sup.2m-1 entries of 00, concatenated with C(2).sup.2m-1 entries of 01, concatenated with C(2).
    Type: Grant
    Filed: August 14, 1987
    Date of Patent: July 25, 1989
    Assignee: International Business Machines Corp.
    Inventor: Robert P. Brinkman
  • Patent number: 4846920
    Abstract: A plasma processing apparatus and process endpoint detection method including a plasma chamber for processing an item that has a first portion of a first material and a second portion of a second material, with the first and second materials having different work functions, and a structure for generating a plasma in the plasma chamber, with the plasma generating structure including at least a pair of RF-power electrodes with one of them being excited by an RF excitation frequency. The apparatus further includes a structure for generating and ejecting electrons from the second material only when the second material is exposed to the plasma, and a structure for increasing the energies of these generated electrons and accelerating these electrons into the etching plasma with sufficient energy to generate secondary electrons in the plasma.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: July 11, 1989
    Assignee: International Business Machine Corporation
    Inventors: John H. Keller, Gary S. Selwyn, Jyothi Singh
  • Patent number: 4839715
    Abstract: An integrated circuit chip including a first and a higher second surface levels with an abrupt sidewall step transition therebetween, and having a first layer of a first conductive material disposed over the first surface level and over the second surface level, but terminating on the first surface level in a first end portion which extends up to but does not touch the sidewall. This end portion comprises a conductive material which has been converted to an insulator. A second layer of a second conductive material is disposed on top of the first conductive layer with essentially no conductive material conversion to insulator therein adjacent to the abrupt sidewall transition. In a preferred embodiment, the conductive material is an alloy of aluminum and the end portion is aluminum oxide.
    Type: Grant
    Filed: August 20, 1987
    Date of Patent: June 13, 1989
    Assignee: International Business Machines Corporation
    Inventors: Joseph J. Gajda, Kris V. Srikrishnan, Paul A. Totta, Francis G. Trudeau
  • Patent number: 4832787
    Abstract: A gas mixture for use in the selective dry etching of a nitride insulator layer relative to an oxide insulator layer comprising: a gas mixture containing chlorine and oxygen. The oxygen in this gas mixture must comprise 15% or less by volume.In a preferred process embodiment for ethcing Si.sub.3 N.sub.4 and leaving a layer of SiO.sub.2 therebelow, Cl.sub.2 gas may be used in combination with 12% or less oxygen by volume. Etch selectivity of greater than five to one is achieved with this gas mixture when a plasma RF frequency of less than 1 MHz is utilized. When a high frequency RF component in the range of 10-27 MHz is added to the RF excitation signal, then an etch uniformity of better than 3% is achieved.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: May 23, 1989
    Assignee: International Business Machines Corporation
    Inventors: James A. Bondur, Francois D. Martinet
  • Patent number: 4833425
    Abstract: A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: May 23, 1989
    Assignee: International Business Machines Corporation
    Inventors: Edward F. Culican, Sr., John D. Davis, John F. Ewen, Scott A. Mc Cabe, Joseph M. Mosley, Allan L. Mullgrav, Jr., Philip F. Noto, Clarence I. Peterson, Jr., Philip E. Pritzlaff, Jr.
  • Patent number: 4825178
    Abstract: An oscillator with noise rejection which may be used in a gate array in a semiconductor chip including a first amplifier circuit, a circuit, for connecting an external feedback element (crystal) across the input and inverting output of the first amplifier circuit for generating and amplifying a sine wave, and a circuit connected to the inverting output of the first amplifier circuit for generating a square wave with the duty cycle thereof being proportional to the difference between the center of the voltage swing of the amplified sine wave and a reference voltage. In a preferred embodiment, the first amplifier circuit and the generating circuit each include a current switch. A voltage reference network is provided to set the reference voltage for the current switch in the generating circuit to the center of the voltage swing of the sine wave applied to that current switch. This results in a 50% duty cycle square wave for the output signal.
    Type: Grant
    Filed: August 26, 1987
    Date of Patent: April 25, 1989
    Assignee: International Business Machines Corporation
    Inventors: Edward F. Culican, John D. Davis, Martin E. Powell, Philip E. Pritzlaff, Jr.
  • Patent number: 4824009
    Abstract: In the process of braze attachment of electronic package members, such as attaching metallic coated connector pins to a multilayer ceramic substrate, contact areas of the substrate are formed by sequential coatings of molybdenum and nickel, which are heated to diffuse the nickel. A pure gold paste is applied by screen printing, for example, followed by the step of firing to burn out the paste binder and to sinter the pure gold particles onto a dense low porosity structure. The sintering operation converts the Ni film into a continuous Au-Ni solid solution. During pin braze, Ni-Sn intermetallics are dispersed in a gold rich matrix of the Au-Ni solid solution.
    Type: Grant
    Filed: December 31, 1981
    Date of Patent: April 25, 1989
    Assignee: International Business Machines Corporation
    Inventors: Raj N. Master, Marvin S. Pittler, Paul A. Totta, Norman G. Ainslie, Paul H. Palmateer
  • Patent number: 4812756
    Abstract: A contactless technique for semiconductor wafer testing comprising: depositing charges on the top surface of an insulator layer over the wafer to create an inverted surface with a depletion region and thereby a field-induced junction therebelow in the wafer, with an accumulated guard ring on the semiconductor surface therearound. The technique further includes the step of changing the depth to which the depletion region extends below the inverted semiconductor wafer surface to create a surface potential transient, and the step of measuring a parameter of the resultant surface potential transient. This technique may be utilized to make time retention and epi doping concentration measurements. It is especially advantageous for reducing the effects of surface leakage on these measurements. In a preferred embodiment, corona discharges are used to effect the charge deposition configuration. Either corona discharge or photon injection are used to change the depletion region depth.
    Type: Grant
    Filed: August 26, 1987
    Date of Patent: March 14, 1989
    Assignee: International Business Machines Corporation
    Inventors: Huntington W. Curtis, Min-Su Fung, Roger L. Verkuil
  • Patent number: 4810962
    Abstract: A voltage regulator for regulating the voltage at a first node, comprisinga first voltage supply;a first node;a first transistor with a control terminal connected to the first node;a circuit for varying the VBE voltage drop of the first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from the first transistor; anda circuit for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.
    Type: Grant
    Filed: October 23, 1987
    Date of Patent: March 7, 1989
    Assignee: International Business Machines Corporation
    Inventors: Gene J. Gaudenzi, Susan L. Tempest
  • Patent number: 4811343
    Abstract: A test circuit for producing a "fail" signal if a clock path driver circuit develops an AC or DC defect. In the simplest embodiment, this test circuit comprises a time delay block for providing a delayed clock signal and its complement, with a delay that exceeds the signal propagation time through the clock receiver and driver; a latch which, in one embodiment, is clocked by the complement of the delayed clock signal to receive the drive signal and to generate pulses which do not overlap in time with the pulses of the delayed clock signal during normal circuit operation; and a gate for detecting such a pulse overlap and for generating an error signal to indicate an AC or DC fault. This circuit effectively detects AC faults at one edge of the clock pulse and one type of DC fault.In a further embodiment of the present invention, this circuit can be combined with a complementary circuit to detect AC faults at both edges of the clock pulse.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: March 7, 1989
    Assignee: International Business Machines Corporation
    Inventors: George T. Johansson, Maureen B. Johansson
  • Patent number: 4809196
    Abstract: A method for marking/sorting semiconductor wafers in accordance with predicted values of oxygen precipitation in the wafers that will occur after the performance of a thermal process step. In a preferred embodiment, this oxygen precipitation prediction is obtained by means of a correlation equationY=A.sub.o +A.sub.1 OX.sub.i +A.sub.2 /LT+A.sub.3 C+A.sub.12 OX.sub.i /LT+A.sub.13 OX.sub.i C+A.sub.23 C/LT,where OX.sub.i is the value of interstitial oxygen in the wafer measured prior to the thermal process step, LT is the minority carrier lifetime for the wafer measured prior to the thermal process step, and C is the initial substitutional carbon in the wafer measured prior to the thermal process step. The constants A.sub.0, A.sub.1, A.sub.2, A.sub.3, A.sub.12, A.sub.23, and A.sub.13 are initialized on a first sample of wafers representative of a desired range of crystal types.
    Type: Grant
    Filed: April 10, 1986
    Date of Patent: February 28, 1989
    Assignee: International Business Machines Corporation
    Inventor: Donald A. Miller
  • Patent number: 4806785
    Abstract: A half current switch comprising: at least one input transistor, a load resistance connected between a first voltage reference and the collector of the input transistor, a constant-current resistance connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor to drive a current through the constant current resistance which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant.
    Type: Grant
    Filed: February 17, 1988
    Date of Patent: February 21, 1989
    Assignee: International Business Machines Corporation
    Inventors: Michel S. Michail, James L. Walsh
  • Patent number: 4798976
    Abstract: A logic redundancy circuit scheme, comprising a plurality of pairs of logic circuit groups, each logic circuit group in a given pair having a respective logic node and a respective power control line, with each logic circuit group in a given pair generating substantially the same logic function signal on its respective logic node as the other logic circuit group in the given pair generates on its respective logic node. The circuit scheme further includes a plurality of isolation circuits having respective output nodes, with a different isolation circuit connected to each different logic circuit group logic node. These isolation circuits are powered at all times and each operates to provide an output signal on its output node indicative of the signal on the logic node connected thereto, while isolating the connected logic node from nets connected to the isolation circuit output node.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: January 17, 1989
    Assignee: International Business Machines Corporation
    Inventors: James J. Curtin, Jack A. Dorler, George J. Jordy, Kenneth L. Leiner
  • Patent number: 4774559
    Abstract: The disclosure is directed to integrated circuit chips and particularly to "gate array", or "master slices" whereon one or more circuits drive a highly capacitive on chip wiring net. The driving circuits are modified and a compensation circuit coupled to the highly capacitive on chip wiring net to mitigate the burden caused by the high capacitance. The integrated circuit structure also contains efficiently positioned on each chip a number of compensation circuits which are readily connectable during the fabrication of the chip. The employment of one, or a number of, on chip compensation circuits does not materially increase the chip power consumption.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: September 27, 1988
    Assignee: International Business Machines Corporation
    Inventors: Edward F. Culican, Philip E. Pritzlaff, Jr.
  • Patent number: 4766399
    Abstract: An oscillator with noise rejection and a fifty percent duty cycle for the on-chip generation and conversion of a sine wave to a square wave, using an external reference crystal. The circuit comprises a low gain current switch including a first and second switching transistors, with the control lines of the switching transistors connected to a reference voltage line. The reference crystal is connected across the control input and the current receiving terminals of the first transistor so that a square wave is obtained at the current receiving terminal of the second transistor. A threshold circuit is included for adjusting the voltage of the square wave signal from the second transistor and applying the adjusted signal to a diode-coupled receiver circuit, which provides the output for the circuit.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: August 23, 1988
    Assignee: International Business Machines Corporation
    Inventors: John D. Davis, Allan L. Mullgrav, Jr.
  • Patent number: 4752813
    Abstract: A Schottky barrier diode and ohmic contact metallurgy which is especially suited for shallow-junction bipolar semiconductor devices. The metallurgy comprises a thin layer of an at least 95 atomic % pure Schottky metal disposed in the contact openings on a shallow-junction semiconductor device to a thickness of less than 850 angstroms. An electrically conducting barrier layer is then disposed over the thin Schottky metal layer, with the barrier layer being of a material which does not react with either the Schottky metal or the semiconductor material in the contact openings to thereby prevent semiconductor material from diffusing past the barrier layer. An electrical contact layer is then deposited over the barrier layer. The doping of the semiconductor material in the individual contact openings determines whether an ohmic contact or a Schottky barrier diode is formed. The resulting ohmic contact metal and Schottky barrier metal do not penetrate through to the shallow junction of the semiconductor device.
    Type: Grant
    Filed: August 8, 1986
    Date of Patent: June 21, 1988
    Assignee: International Business Machines Corporation
    Inventors: Harasaran S. Bhatia, Satya P. Bhatia, Cyril P. de Vries, Douglas A. Grose
  • Patent number: H1754
    Abstract: A new method for preparing low loss multimode and monomode glass optical fibers which avoids casting or pouring the core and clad melts is disclosed. The new technique is based on a reactive-gas-transport approach which avoids contamination from absorbing impurities and scattering centers by reacting the glass melt with reactive gases which remove impurities and increase the refractive index of the fiber.
    Type: Grant
    Filed: December 13, 1985
    Date of Patent: October 6, 1998
    Assignee: United States of America
    Inventors: Danh C. Tran, George H. Sigel, Jr.