Patents Represented by Attorney William T. Ellis
  • Patent number: 4746817
    Abstract: A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits.
    Type: Grant
    Filed: March 16, 1987
    Date of Patent: May 24, 1988
    Assignee: International Business Machines Corporation
    Inventors: Dennis C. Banker, Allan H. Dansky, Jack A. Dorler, Walter S. Klara, Frank M. Masci, Steven J. Zier, Adrian Zuckerman
  • Patent number: 4746815
    Abstract: A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.
    Type: Grant
    Filed: July 3, 1986
    Date of Patent: May 24, 1988
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Mario E. Ecker, Harry J. Jones, Shashi D. Malaviya
  • Patent number: 4743781
    Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.
    Type: Grant
    Filed: July 3, 1986
    Date of Patent: May 10, 1988
    Assignee: International Business Machines Corporation
    Inventors: Harsaran S. Bhatia, Harry J. Jones, Shashi D. Malaviya
  • Patent number: 4740968
    Abstract: A circuit for quickly determining if all of the data bits in an ECC word are correct and/or for detecting failures in an error detection syndrome generation path in an ECC circuit, where the ECC circuit utilizes an error correction code with two diagonal quadrants in the code matrix composed entirely of columns which have an even number of ones, and with the other two quadrants composed entirely of columns which have an odd number of ones.In one embodiment, the circuit comprises means for generating a parity bit, P.sub.k, for each of K data fields in the ECC word; means for comparing logical combinations of these parity bits to logical combinations of the memory check bits, C.sub.j, to form H bits; and means for logically combining these H bits to form a D bit. This D bit may be compared to the binary (non-carry) sum of the syndrome bits to detect syndrome generation path failures.
    Type: Grant
    Filed: October 27, 1986
    Date of Patent: April 26, 1988
    Assignee: International Business Machines Corporation
    Inventor: Frederick J. Aichelmann, Jr.
  • Patent number: 4731158
    Abstract: A method and means for high-rate etching a material is disclosed including the steps of disposing a gas mixture of a fluorine-containing molecule and H.sub.2 over the surface of a material to be etched; and laser dissociating this fluorine-containing molecule in the gas mixture to cause very fast etching of the material surface. In a preferred embodiment, the fluorine-containing molecule is chosen from the group of NF.sub.3, SF.sub.6, and COF.sub.2, and the surface to be etched is unmasked silicon.
    Type: Grant
    Filed: September 12, 1986
    Date of Patent: March 15, 1988
    Assignee: International Business Machines Corporation
    Inventor: James H. Brannon
  • Patent number: 4729006
    Abstract: A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.
    Type: Grant
    Filed: March 17, 1986
    Date of Patent: March 1, 1988
    Assignee: International Business Machines Corporation
    Inventors: Anthony J. Dally, Seiki Ogura, Jacob Riseman, Nivo Rovedo
  • Patent number: 4728814
    Abstract: An impulse generator for detecting an edge of an input pulse. The impulse generator comprises a first and second transistors connected to turn on at the occurrence of a signal pulse on an input line, with the second transistor connected to operate in its inverse mode so that it has a longer turn-on time. The second transistor is connected in such a manner as to draw current away from the base of the first transistor when the second transistor turns on, thereby causing an impulse to be generated at the output terminal of the first transistor, regardless of the width of the input pulse.
    Type: Grant
    Filed: October 6, 1986
    Date of Patent: March 1, 1988
    Assignee: International Business Machines Corporation
    Inventor: George E. Smith, III
  • Patent number: 4721689
    Abstract: A method for simultaneously forming a level of interconnection metallurgy over, and inter-level via studs through, an insulating layer of a semiconductor chip. The method comprises the steps of forming a plurality of via holes in the insulating layer, high-mobility sputtering conductive material on to the surface of the insulating layer and into the via holes therein, masking the conductive material layer, and then ion beam milling through the mask to form a patterned interconnection layer. The high-mobility sputtering step is accomplished by reducing the background pressure to below 10.sup.-7 Torr to eliminate non-mobile species, maintaining a sputter pressure of less than 7 microns, maintaining an appropriate chip bias level to keep the conductive material molecules mobile until they reach their lowest energy state, and maintaining the temperature of the chip at a level so that a high sputter species mobility is maintained.
    Type: Grant
    Filed: August 28, 1986
    Date of Patent: January 26, 1988
    Assignee: International Business Machines Corporation
    Inventors: Paul N. Chaloux, Jr., Thomas F. Houghton, Richard K. West
  • Patent number: 4713140
    Abstract: An apparatus and method for monitoring a change of thickness of a first material with a first bandgap energy, for disposal over a second material on a wafer and having a second different bandgap energy, wherein at least one of the materials has a direct bandgap. The apparatus comprises means for changing the thickness of the first material layer; means for directing a beam of energy to impinge at an angle on to the surface and to penetrate the wafer, with the beam having an energy sufficient to pump the at least one direct bandgap material to a higher energy state; and means for detecting the induced luminescence from the at least one direct bandgap material to determine when to alter the thickness changing process.The present invention may be used to monitor both deposition and etching processes. It is particularly suited for determining the etch endpoint for III-V semiconductor materials such as GaAs and AlGaAs.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: December 15, 1987
    Assignee: International Business Machines Corporation
    Inventor: Zu-Jean Tien
  • Patent number: 4709169
    Abstract: A logic circuit network with circuitry for independently controlling at least one of the logic levels generated thereby, comprising, in one embodiment, a logic circuit with an output current node, a complement output current node, and at least one input line, the circuit for generating an output voltage level at the output current node which depends on the amount of current drawn therethrough, and for generating a complement output voltage level at the complement output current node which depends on the amount of current drawn therethrough; in combination with a current drawing means for drawing a controlled amount of current through one of those nodes to adjust the voltage level at that node. In one embodiment, this current drawing means is connected to a voltage reference level V.sub.R1, and operates to draw an amount of current from whichever current node is at a voltage level which is closest to a predetermined constant plus this voltage reference level V.sub.R1.
    Type: Grant
    Filed: September 2, 1986
    Date of Patent: November 24, 1987
    Assignee: International Business Machines Corporation
    Inventors: Gerard J. Ashton, Joseph R. Cavaliere, Ming T. Cheng
  • Patent number: 4708941
    Abstract: A device for detecting small amounts of alkanes such as methane, ethane, propane, and butane gases, comprising an optical waveguide and a light source for propagating light therethrough; apparatus for obtaining samples of air to be tested; apparatus for adding water vapor to these air samples to yield gas mixtures with at least a 30% relative humidity; and means for flowing these mixtures over the surface of the optical waveguide at a rate sufficient to favor condensation of the mixture on the waveguide surface to thereby form a thin film thereon. The presence of alkanes is determined by detecting the intensity of the light after propagation through the optical waveguide and then comparing that detected intensity to a reference. In a preferred embodiment, the optical waveguide is an optical glass capillary in which the surface is closed in a lens-like configuration at the detector end.
    Type: Grant
    Filed: March 7, 1985
    Date of Patent: November 24, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: John F. Giuliani
  • Patent number: 4694433
    Abstract: A memory structure for very large memory arrays on a chip is described where the memory array is divided into a number of subarrays. The subarrays are controlled via common word decoders and subarray decoders. The word lines of the individual subarrays are individually selectable through word line switches, and the bit lines of the subarrays are applied directly to a common line system, and interconnected in such a manner that the peripheral circuits, e.g. the data input and output circuits, can be arranged in practically any free location on the chip.
    Type: Grant
    Filed: April 4, 1985
    Date of Patent: September 15, 1987
    Assignee: International Business Machines Corporation
    Inventor: Siegfried K. Wiedmann
  • Patent number: 4684339
    Abstract: A gas-loaded diaphragm for exerting a predetermined pressure on a ceramic substrate during sintering to prevent x-y shrinkage. In the most preferred embodiment, the diaphragm comprises a gas-filled base composed of two opposing discs, and a substantially hollow gas-filled toroid container disposed around the perimeter of the opposing discs and communicating therewith to permit gas flow therebetween. This diaphragm is disposed in relation to a ceramic substrate-containing cell so that when it is heated to a desired temperature, the gas in the diaphragm expands and forces the two opposing discs apart to thereby exert a predetermined pressure on the ceramic substrate-containing cell.
    Type: Grant
    Filed: June 13, 1986
    Date of Patent: August 4, 1987
    Assignee: International Business Machines Corporation
    Inventors: Raschid J. Bezama, Charles H. Perry
  • Patent number: 4678267
    Abstract: Coupling between narrow-and wide-channel optical waveguides is found to be very efficiently performed by coupling regions in the form of parabolas. Design equations for parabolic coupling regions are given.
    Type: Grant
    Filed: June 30, 1981
    Date of Patent: July 7, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: William K. Burns, A. Fenner Milton
  • Patent number: 4675072
    Abstract: Laser induced fluorescence is utilized to detect and control the reactive ion etch-through of a given layer in a wafer by detecting a large change in the concentration of a selected minor species from the wafer in the etching plasma. This selected minor species must be present in a significantly different concentration in the etched given layer compared to adjacent layers in the wafer in order to provide a proper endpoint detection. In one embodiment, when the large change in the selected minor species concentration is detected, then the RF electrodes for the reactor are automatically de-energized.
    Type: Grant
    Filed: June 25, 1986
    Date of Patent: June 23, 1987
    Assignee: International Business Machines Corporation
    Inventors: Reid S. Bennett, Linda M. Ephrath, Geraldine C. Schwartz, Gary S. Selwyn
  • Patent number: 4661789
    Abstract: A broadband microwave recursive filter that provides sharp transitions in the frequency domain between adjacent stop and passbands comprising a signal input node; a signal output node; a filter circuit connected between the signal input node and the signal output node for providing a signal flow therebetween which has a predetermined frequency bandwidth characteristic; a microwave transistor circuit, with the microwave transistor circuit being band-limited to provide gain in only a restricted window of frequencies within the predetermined frequency bandwidth and connected for providing amplification to signals flowing in the filter circuit between the signal input node and the signal output node while suppressing out-of-window signals resulting from design approximations.
    Type: Grant
    Filed: July 17, 1985
    Date of Patent: April 28, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Christen Rauscher
  • Patent number: 4659423
    Abstract: An improvement in the method and apparatus for growing a semiconductor crystal by the Czochralski technique comprising the steps of applying a rotating transverse magnetic field to molten semiconductor material held in a crucible during the seed crystal pulling and crystal formation step, to cause the molten material to rotate within the crucible, and simultaneously increasing the rotational velocity of the magnetic field during this crystal formation as a function of the length of the crystal pulled from said molten material to thereby vary the rotation rate of the molten material. These steps result in the uniform axial distribution of oxygen in the crystal.
    Type: Grant
    Filed: April 28, 1986
    Date of Patent: April 21, 1987
    Assignee: International Business Machines Corporation
    Inventors: Kyong-Min Kim, Pavel Smetana, Wolfgang A. Westdorp
  • Patent number: H290
    Abstract: In a modified Betatron a low density background plasma is maintained in the vacuum chamber causing image charges in response thereto to form in the chamber wall. These image charges cause the self forces of the electron beam being accelerated in the betatron to be directed inward in the polodial plane thus eliminating injection problems, the diamagnetic to paramagnetic transition, and the l=2 resistive wall instability.
    Type: Grant
    Filed: December 10, 1985
    Date of Patent: June 2, 1987
    Assignee: United States of America
    Inventor: Wallace M. Manheimer
  • Patent number: H291
    Abstract: A method of making a planar junction field-effect transistor in which a semi-insulating substrate of a III-V semiconductor, particularly InP, is ion implanted by two ions to produce both an n-type region and a p-type region. The gate is further defined by selectively etching through the gate-implant region to the source/drain channel.
    Type: Grant
    Filed: May 7, 1986
    Date of Patent: June 2, 1987
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: John B. Boos
  • Patent number: H474
    Abstract: A method and means for forming an optical transversal filter and the optical transversal filter itself. The optical transversal filter comprises an optical fiber with a plurality of short reflective phase gratings disposed therein, with each reflective phase grating comprising a periodic variation of the refractive index of the optical fiber. These reflective phase gratings are disposed at predetermined positions along the length of the optical fiber and each reflective phase grating has a predetermined reflectance in order to reflect a predetermined relative amplitude of the light propagating in a first direction within the optical fiber to thereby counterpropagate back along the optical fiber. Modulated light source means are provided for directing light into one end of the optical fiber, and means for detecting light are provided to detect the light reflected by the plurality of reflective phase gratings.
    Type: Grant
    Filed: October 25, 1985
    Date of Patent: June 7, 1988
    Assignee: United States of America
    Inventor: Henry F. Taylor