Abstract: A device for detecting and/or measuring the presence of a magnetic vector potential "field" including two Josephson devices in a Josephson interferometer configuration, a magnetic shielding envelope with apertures arranged so that the magnetic vector potential is confined to the vicinity of one of the two Josephson devices (but not the interferometer loop region) and a means for detecting magnetic flux induced by the interaction of the Josephson device and the magnetic vector potential "field". The detection of the magnetic vector potential offers a more advantageous range of dependence than the magnetic flux density.

Abstract: Apparatus for implementing a single computer instruction for moving a binary number of from one to four characters, with the characters of a given binary number having either eight or nine bits per character, from storage in a word addressable memory to a designated addressable register. The characters of the binary number are stored in the word addressable memory with each word of memory being divided into four 9-bit bytes. The most significant character of the binary number can be stored in any designated byte position of a word location with the characters of the number stored in contiguous byte locations in descending order of significance. The apparatus causes the binary number to be stored in the designated addressable register with the binary number being right justified in that register. Higher order bit positions of the register not needed to store the bits of the binary number will have stored into them fill bits or the sign bit of the number.

Abstract: In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.

Abstract: A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage locations, the contents of the second multiplicity of storage locations adapted for addressing the first multiplicity of storage locations, a counter for addressing the second multiplicity of storage locations; and control logic for controlling the counter and entry and withdrawal of data signals in the first and second multiplicity of storage locations.

Abstract: An apparatus and method for encoding information receiving a binary information stream. The apparatus actuates one of four outputs as determined by the last output actuated and the binary level of the binary bit received.

Abstract: There is disclosed herein an apparatus for displaying data and communicating with another data processing device via a parallel port or over a long distance communications network via a full duplex modem, said computer terminal utilizing a microprocessor for programmed control of the terminal. The terminal is capable of displaying information on a standard black and white television set and utilizes a keyboard for entering information to be displayed or sent to the main data processing system. Limited graphics with sixty four graphics patterns are also available by using the microprocessor chip to scan the keyboard and communicate with the modem and parallel ports, and by utilizing a standard television set instead of a cathode ray tube, substantial material cost savings can be made in building the terminal which could be built for under $250 in parts in 1979.

Abstract: A control apparatus for a switching regulator circuit having a voltage controlled oscillator responsive to any deviation of the output voltage of the switching regulator circuit from a predetermined reference voltage. The voltage controlled oscillator produces a digital pulse stream having a frequency which is varied by the voltage controlled oscillator in response to any deviation of the output voltage of the switching regulator circuit from the predetermined reference voltage. A recovery detector is connected to at least one of the reactors of the switching regulator circuit to ensure that the particular SCR associated with that reactor has fully recovered prior to the next actuation thereof. If the particular SCR has not recovered then the digital pulse which would be distributed to that SCR within the digital pulse stream is held.

Abstract: A switching regulator circuit for utilization with power supplies supplying a high DC output current including a plurality of control rectifiers and inductive reactors with sequential gating of the rectifiers at regular intervals for providing overlapped output current pulses from the reactors. An output circuit receives the rippled current comprised of the overlapped output current pulses for reducing the ripple therein. The output circuit includes a choke in series with the output which induces phase shift between the rippled current and the output current. A sensing winding associated with the choke eliminates the phase shift voltage for forming a feedback signal as an input to a control circuit. The control circuit utilizes the feedback signal to control the rate at which the rectifiers are gated sequentially.

Abstract: Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.

Abstract: An apparatus for calibrating a test unit adapted to characterize CML integrated circuits. The apparatus is adapted to deskew the time delays of each pin of the fixture which receives the CML circuit under test with respect to a certain predetermined pin and preselected pin thereof. The preselected pin and a predetermined pin are shorted and the time delay between the generation of a shaped pulse and its connection through the preselected pin to the predetermined pin and to a test unit is determined by said test unit. The time delays are then utilized to remove any time delays caused by the test apparatus itself so that the CML circuit under test can be accurately characterized.

Abstract: A testing apparatus for CML integrated circuits having a power splitter connected at its input to a pulse generator, and at one output to a test unit and at its other output to the CML circuit through a matrix. The output waveform of the CML circuit is provided through the matrix to the test unit.

Abstract: In a microprogrammed data processing system in which the boundaries of the operands or data strings identified by the descriptors are not constrained to coincide with boundaries of the units of addressable memory space, i.e., words, the time required to retrieve, execute and store operands of a three descriptor instruction, wherein two descriptors define the memory address of the initial operands and the third descriptor defines the memory address of the resulting operand, can be reduced by prefetching the two words which include the boundaries of the operand (data string) identified by the third descriptor. After execution of the instruction, the boundary words of the resulting operand (data string) can have the rewrite data, that is the data of the boundary words which are not part of the resulting operand, and should therefore be retained and inserted in appropriate positions of the appropriate boundary word by a retrieval of the boundary words which do not interrupt the normal data processing sequence.

Abstract: There is disclosed herein an apparatus for computerized real time verification of the correctness of pin locations for wire wrap connections made by human operators in constructing or upgrading computer backplanes. A suitably programmed microprocessor operates from a data base consisting of the information from a wire list drawing fed into the microprocessor's memory from a cassette tape record. The microprocessor is linked to the backplane to be verified and to the hand operated wire wrap gun serving as the test probe by a uniquely designed Wire Check System Interface. Both wire adds and wire deletes may be made.

Abstract: There is disclosed herein an apparatus for verifying the correct placement of a wire wrap tool on a wire wrap pin in an array of pins. An outside source of pin and condition data such as a human operator operating switches or a mechanical sequential state machine or a hand wired logic sequential state machine supplies binary data indicating the correct pin and the expected electrical condition to be found on the correct pin. A wire check system interface means in combination with a wire wrap tool, a strip switch and a number of HDMUG logic boards then subject the correct pin to the expected electrical condition and compare the electrical condition on the pin actually touching the wire wrap tool to the expected electrical condition and signals the correctness or incorrectness of placement of the wire wrap tool.

Abstract: An improved large capacity air distribution system for cooling electronic components mounted on printed circuit boards. The system has an air plenum chamber of substantially constant rectangular cross section. Openings are formed in the side walls of the chamber to permit air from within the chamber to flow outwardly in a direction substantially normal to the outer surfaces of the side walls and over the components to be cooled. A baffle in the form of a tapered wedge formed from a pair of thin metal baffle sheets is mounted in the plenum chamber so that the joined edges of the metal baffle sheets are positioned centrally in the air inlet of the chamber and the baffle is otherwise symmetrically disposed in the chamber. A large number of small round holes are formed through the sheets of the baffle, the area of the holes occupying a substantial percentage, approximately 36 percent, of the total area of the baffle. A high capacity air pump supplies air under pressure to the interior of the plenum chamber.

Abstract: A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.

Abstract: Information from a main data processor is transferred to an auxiliary data processor of the system and is stored in a control file which may be addressed by either a firmware word from a control store or by use of the function code received in an instruction from the main processor. Information in such control file is used for the purpose of addressing main memory. The address for main memory may be incremented or decremented simultaneously as operands are being fetched from main memory for execution.

Abstract: This relates to an apparatus for performing single error correction, double error detection of binary words, each section of the apparatus processing one byte of raw data. Each section includes first logic means for producing a first plurality of intermediate sector matrix parity outputs. A second logic means receives one of the first plurality of intermediate sector matrix parity outputs and a second plurality of intermediates matrix parity outputs from other sections and generates therefrom a syndrome signal. A third logic means receives this syndrome signal and syndrome signals from other sections and generates therefrom the corrected data bits.

Abstract: Apparatus for cutting segments from a strip of film and for mounting the segments in reusable fixtures. Each segment is severed from the strip and mounted in a single cycle of operation of the apparatus. A cutting die is provided with a nonlinear symmetrical cutting edge lying in a die cutting plane. A punch is provided with a bottom surface substantially the size of a segment. The cutting plane of the punch has a linear punch cutting edge formed at the intersection of the bottom surface and the punch cutting plane, and the punch is mounted in cutting relationship with the die. Positioning means position the strip so that a boundary between segments lies in the die cutting plane. As the punch moves toward the die and a fixture located below the die, a segment is severed from the strip by the cutting action of the punch and die cutting edges which co-operate to minimize the forces applied to the segment tending to change the orientation of the segment to the punch.

Abstract: A reusable fixture for a segment of a film strip having a flexible beam lead frame mounted on the segment and an integrated circuit chip bonded to the inner portions of the leads of the lead frame. The fixture is made from an integral laminar layer of a suitable material. The improvements are in providing a plurality of pairs of projections with protuberances which overlie, to a slight degree, the attachment webs of a segment. The fixture is also provided with detachment openings to provide access to the attachment webs which detachment openings facilitate removal of a segment from the fixture.