Abstract: A method of protecting from physical damage the upper surface of medium and large scale integrated IC circuit chips. Certain types of IC chips are provided with a plurality of input/output terminals, or bumps, which project above the upper surface of the chips on which they are formed. The upper surface of each such chip, including its bumps, are spin coated with a thin adhesion promoter which is then dried. The chips and its terminals are next spin coated with a layer of a heat curable resin which is partially cured. The resin and the adhesion promoter are then removed from the upper surfaces of the bump by rubbing with a soft abrasive material. The resin remaining on each IC chip is then finally cured.

Abstract: An apparatus for detecting each short circuited diode in a plurality of diodes, coupled in a parallel combination, is disclosed. The apparatus utilizes a flashing light emitting diode to indicate whether the particular diode under test is shorted or not. By utilizing the series inductance associated with each diode circuit, effective isolation of the particular diode under test is obtained for a short duration test pulse and allows the appropriate test to be made.

Abstract: This relates to an apparatus for assigning priority to information temporarily stored in memory controller stack. Associated with each level of the stack is a counter which measures the length of time the information has been stored. A plurality of comparators and associated control logic determines the stack level which contains information which has been stored the longest. If the destination memory associated with the contents of this level becomes available, this level is given priority with respect to transmission to its destination memory.

Abstract: In an information handling system in which a cyclic code is utilized to both detect and correct errors and a cyclical redundancy code is used for supplementary detection of errors, the cyclical redundancy code (CRC) polynomial is chosen to be a factor of the generator polynomial, g(x), of the error detection and correction (EDAC) code. In this way, the same check bits in the code word used for error detection and correction may be further utilized for a CRC check to supplement the error detection capabilities of the system. The risk of miscorrection of data is reduced to de minimus levels by the partitioning of data and count fields in the course of the development of the error detection and correction codes. Practice of the teachings herein disclosed provides a more efficient error detection and correction system with greatly reduced risk of miscorrection. An embodiment of the invention is disclosed following the methodology taught herein.

Abstract: An improved high current low voltage switching regulator power supply in which the major heat producing components of the power modules of the power supply are mounted on a pair of chill plates with a liquid cooled heat exchanger between the plates. The chill plates are electrically isolated from each other and the heat exchanger. One chill plate also serves as the positive power output bus and the other as the negative power output bus of the power supply which significantly reduces the parasitic inductance of the power supply.

Abstract: Apparatus for cutting and removing layers of photoresist overlaying tooling holes in a printed wire board blank. A lower cutter is mounted on a base so that its cutting edge projects above the upper surface of the base a distance substantially equal to the thickness of a layer of photoresist. A cutter head is mounted on the base for movement parallel to the upper surface of the base. An upper cutter is mounted on the cutter head for movement by a cutter actuator to cause the upper and lower cutters to sever segments of layers of photoresist overlaying a tooling hole of a PWB blank positioned between them. Each cutter is provided with a plunger movable within their respective cutters. The upper surface of the lower plunger, when the lower plunger is retracted, projects above the lower cutting edge of the lower cutter; and the upper plunger is biased downwardly so that its bottom surface projects below the cutting edges of the upper cutter.

Abstract: A multiple bit deskew buffer while providing skew correction for multi-track data read on mass storage devices is disclosed. All data transfers are synchronized to one basic clock eliminating the multiple clocking systems utilized in the prior art. The invention is arranged such that it could be easily modified so as to vary the number of bytes of data held in the byte buffer by either hardware, firmware, or software means.

Abstract: A fluid cooling system for electronic systems particularly adapted to cool large scale integrated circuit chips mounted on substrates. The system has one or more heat exchangers through which a liquid coolant is circulated. Each heat exchanger has a flexible wall and is mounted so that its flexible wall is in close proximity to a surface of the substrate to be cooled. A low thermal impedance contact is made through the flexible wall of the heat exchanger between the substrate to be cooled and the coolant flowing through the heat exchanger because of the pressure of the coolant in the heat exchanger. The heat exchangers are connected into the cooling system through flexible conduits so that a heat exchanger can readily be moved out of contact with a substrate without disrupting the flow of coolant through the cooling system.

Abstract: A digital data recovery apparatus for extracting phase encoded data from mass storage devices is disclosed. By selective strobing of the data string at a frequency determined by the incoming data rate of data already read, a continuously updated data "window" is generated. The data synchronization, clock control and frequency averaging of the previously read data is accomplished without the use of any analog circuitry.

Abstract: Apparatus for blanking an integrated circuit (I.C.) chip and the chip's thin flexible ductile leads which extend beyond the four sides of each chip from a segment of film to which the leads are attached and forming the leads including forming a foot at the free end of each lead of the chip in a single operation of a hollow punch having contiguous cutting and forming edges with a contiguous forming surface between them and a hollow die having cutting edges with a forming block having contiguous forming edges and forming shoulders positioned within the die. The punch and die are mounted on a punch press. Alignment means accurately position the chip and its leads with respect to the punch and die. A pressure pad is mounted in the punch and presses the leads against a portion of the forming block to isolate the bonds between the leads and the integrated circuit chip from forces applied to the leads during cutting and forming.

Abstract: Data stored in a selected block of a memory associated with a data processing system is protected while a first device has access to any memory location in the selected memory block. If another device seeks access to the selected block of memory for the purpose of performing one or more predetermined unique sequences of operation while the first device is carrying any of such operations with respect to the selected memory block, the other device is locked out by means of a signal instructing it to abort the operation for which access is sought. Upon completion of the operation sequence by the first device, the selected memory block is unlocked and access is again available to any device. Further, a device addressing a location of memory for the purpose of carrying out one of a plurality of predetermined unique sequences is informed of the occurrence of events of significance to it by forcing an address register to a predetermined memory location comprised of a plurality of interrupt cells.

Abstract: A 5-bit D-type master/slave counter/shift register with buffered outputs is disclosed. The counter implements the load, count up, count down, and reset functions and also has the capability to be reconfigured into an inverting serial shift register for Non-Functional Test (NFT) techniques. In addition, the fifth bit may optionally be removed from the counter logic and used as a parity bit, although it will be necessary to use some external logic to implement this parity function.

Abstract: In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit. Page tables are set up in memory containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit can locate its assigned page table, and page table words therein are combined with other control words to access paged memory locations.In one mode of operation an extended addressing mechanism is provided which allows the generation of absolute addresses of paged memory locations having an address field larger than the address field of the control words used to access such paged memory locations.

Abstract: Today's cathode ray tube oscilloscopes are widely used throughout the world and form an important basic tool in many industries. An apparatus to modulate the cathode ray display intensity, thereby enhancing the oscilloscope's capabilities in that it can now make more accurate measurements and, in effect, increase its band width, is disclosed. The apparatus to facilitate this effect is light weight, low cost, and easily connected to almost all oscilloscopes now in use.

Abstract: A charge-coupled device (CCD) for amplifying and accumulating charge comprises a first CCD line, a plurality of time-independent CCD charge amplifiers each having an input gate connected to a surface potential tap on a respective one of the charge storage regions of the first CCD line, and a second CCD line for accumulating the charge which has been amplified by the charge amplifiers. The device permits the coherent accumulation of the charge in a time-independent manner. Arithmetic, logic, and complex signal processing functions may be conducted by suitable configurations of the charge amplifiers.

Abstract: A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes.