Patents Represented by Attorney Williams, Morgan & Amerson, P.C.
  • Patent number: 8147670
    Abstract: The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is done by adjustments of corrections factors for currents of a plating tool in a multi-anode configuration. The described method enables control of recipes with different current ratios in each recipe step and models different deposition sensitivities in each recipe step. Generally, the method of the present disclosure requires a measurement step, where the tool state is determined, and a data processing step, where the correction factors are set based on models describing the plating process and the tool state.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: April 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sylvia Boehlmann, Dirk Wollstein, Susanne Wehner
  • Patent number: 8149384
    Abstract: A method for monitoring a photolithography system includes defining a model of the photolithography system for modeling top and bottom critical dimension data associated with features formed by the photolithography system as a function of dose and focus. A library of model inversions is generated for different combinations of top and bottom critical dimension values. Each entry in the library specifies a dose value and a focus value associated with a particular combination of top and bottom critical dimension values. A top critical dimension measurement and a bottom critical dimension measurement of a feature formed by the photolithography system using a commanded dose parameter and a commanded focus parameter are received. The library is accessed using the top and bottom critical dimension measurements to generate values for a received dose parameter and the received focus parameter.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 3, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Siddharth Chauhan, Kevin R. Lensing, James Broc Stirton
  • Patent number: 8143132
    Abstract: In sophisticated semiconductor devices, the threshold voltage adjustment of high-k metal gate electrode structures may be accomplished by a work function metal species provided in an early manufacturing stage. For this purpose, a protective sidewall spacer structure is provided, which is, in combination with a dielectric cap material, also used as an efficient implantation mask during the implantation of extension and halo regions, thereby increasing the ion blocking capability of the complex gate electrode structure substantially without affecting the sensitive gate materials.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: March 27, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Jan Hoentschel, Sven Beyer, Thilo Scheiper
  • Patent number: 8138050
    Abstract: Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: March 20, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vassilios Papageorgiou, Jan Hoentschel, Robert Mulfinger, Casey Scott
  • Patent number: 8138038
    Abstract: In a replacement gate approach, a top area of a gate opening may receive a superior cross-sectional shape after the deposition of a work function adjusting species on the basis of a polishing process, wherein a sacrificial material may protect the sensitive materials in the gate opening.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: March 20, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Gerd Marxsen, Katja Steffen
  • Patent number: 8138571
    Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 20, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg, Frank Wirbeleit, Karla Romero
  • Patent number: 8140159
    Abstract: A method, system, and apparatus for implementing a safe mode operation of an implantable medical system using impedance adjustment(s) are provided. A first impedance is provided to a lead. An indication of a possibility of a coupled energy is received. Based upon said indication, a second impedance associated with the lead to reduce the coupled energy is provided.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 20, 2012
    Assignee: Cyberonics, Inc.
    Inventors: Dana Michael Inman, Randolph K. Armstrong, Scott A. Armstrong
  • Patent number: 8137818
    Abstract: Herein disclosed is a composition containing from about 5 weight parts to about 50 weight parts of a branched polylactic acid; from about 50 weight parts to about 95 weight parts of water; and from about 0.1 weight parts to about 1 weight part of a first surfactant. The composition can be coated onto a substrate containing paper or paperboard and having a first surface and a second surface, to form a paper product having oil, grease, and moisture resistance.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: March 20, 2012
    Assignee: Tate & Lyle Ingredients Americas LLC
    Inventors: Michael D. Harrison, Geoffrey A. R. Nobes, Penelope A. Patton, Shiji Shen, Henk Westerhof
  • Patent number: 8133164
    Abstract: A system for well fluid treatment, the system being transportable, the system including a base, a support structure on the base, a brace apparatus connected to the base and to the support structure for bracing the support structure during movement of the system, the brace apparatus releasably secured to the support structure and releasably secured to the base, at least one holding tank on the base for holding well fluid to be treated, from an active rig well fluid system and the well fluid to be treated including solids, centrifuge apparatus for centrifuging a mixture of well fluid and solids from the at least one holding tank, producing reusable fluid, a first pump apparatus for pumping well fluid and solids from the at least one holding tank to the centrifuge apparatus, and a centrifuge support on the base for supporting the centrifuge apparatus.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: March 13, 2012
    Assignee: National Oilwell Varco L.P.
    Inventors: Randy Charles Beebe, Donald Tracey Crosswhite, Larry Jona Kellert, James Joseph Tait, Dean Mitchell Bird
  • Patent number: 8134953
    Abstract: The present invention provides a method of determining characteristics of access classes in a wireless communication system. In one embodiment, a method is provided for implementation in an access network of a wireless communication system. The method includes mapping, at the access network, a plurality of priority levels to a plurality of access classes. Each access class is associated with at least one parameter used by access terminals to establish a wireless communication link with the access network. The method also includes transmitting, from the access network to a first access terminal, information indicating the mapping of the plurality of priority levels to the plurality of access classes in response to receiving a request to establish a communication session between the first access terminal and the access network.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: March 13, 2012
    Assignee: Alcatel Lucent
    Inventors: Christopher F. Mooney, David A. Rossetti, Jialin Zou
  • Patent number: 8135962
    Abstract: A memory, system, and method for providing security for data stored within a memory and arranged within a plurality of memory regions. The method includes receiving an address within a selected memory region and using the address to access an encryption indicator. The encryption indicator indicates whether data stored in the selected memory page are encrypted. The method also includes receiving a block of data from the selected memory region and the encryption indicator and decrypting the block of data dependent upon the encryption indicator.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 13, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Geoffrey S. Strongin, Brian C. Barnes, Rodney Schmidt
  • Patent number: 8129236
    Abstract: After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 6, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andreas Gehring, Anthony Mowry, Andy Wei
  • Patent number: 8129276
    Abstract: In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: March 6, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Ralf Richter, Kai Frohberg, Holger Schuehrer
  • Patent number: 8127057
    Abstract: An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory accessed by speculative memory access operations and to retain the data during at least a portion of an attempt to execute the atomic memory transaction. The apparatus also comprises an overflow detection circuit configured to detect an overflow condition upon determining that the data cache has insufficient capacity to buffer a portion of data accessed as part of the atomic memory transaction, as well as a buffering circuit configured to respond to the detection of the overflow condition by preventing the portion of data from being buffered in the data cache and buffering the portion of data in a secondary buffer separate from the data cache.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: February 28, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jaewoong Chung, David S. Christie, Michael P. Hohmuth, Stephan Diestelhorst, Martin Pohlack
  • Patent number: 8124467
    Abstract: In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon layer may be formed on the silicon/germanium alloy, possibly including a further strain-inducing atomic species other than germanium, in order to provide a high strain component while also providing superior conditions during the silicidation process.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: February 28, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Vassilios Papageorgiou, Maciej Wiatr
  • Patent number: 8124532
    Abstract: By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous ambient on the basis of tin hydride and nickel, carbon monoxide in a thermally driven reaction.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: February 28, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christof Streck, Volker Kahlert, Alexander Hanke
  • Patent number: 8119461
    Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: February 21, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Martin Trentzsch, Thorsten Kammler, Rolf Stephan
  • Patent number: 8118932
    Abstract: By locally heating specific scan positions within a region of interest and automatically obtaining respective measurement data in a time-resolved and spatially-resolved fashion, dynamic processes within a metallization layer of semiconductor devices may be efficiently monitored and/or modified. For instance, OBIRCH and SEI techniques may be used in combination with the automated data recording and manipulation, thereby providing an efficient means for in situ failure analysis, defect identification, for any dynamic degradation processes in interconnects and interlayer dielectrics.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: February 21, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Buschbeck, Eckhard Langer, Marco Grafe
  • Patent number: 8118172
    Abstract: A screening apparatus for separating components of a material by vibratory separation which, in certain aspects, includes a vibratable box connected via vibration isolators within a container, the box including screening apparatus thereon or the vibratory separator having replaceable screening cartridges within a container. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b).
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 21, 2012
    Assignee: National Oilwell Varco L.P.
    Inventor: George Alexander Burnett
  • Patent number: 8117548
    Abstract: A method, apparatus, and system are provided for displaying a graphical representation of at least a portion of a file by interfacing with a graphical interface relating to the file. A request for viewing a file content is received. A window for viewing a graphical representation of at least a portion of the content of a file is provided.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: February 14, 2012
    Assignee: Apple Inc.
    Inventor: Gene Z. Ragan