Abstract: A plurality of field emission device cathodes each generate emission of electrons, which are then controlled and focused using various electrodes to produce an electron beam. Horizontal and vertical deflection techniques, similar to those used within a cathode ray tube, operate to scan the individual electron beams onto portions of a phosphor screen in order to generate images. The use of the plurality of field emission cathodes provides for a flatter screen depth than possible with a typical cathode ray tube.

Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.

Abstract: A system and method for routing the maximum number of trunks on a network with resource constraints is described. The invention provides a unique modification of a multi-commodity mathematical model that maximizes flow in a capacity constrained network. The problem of routing the maximum number of trunks through a communications network can be described as a multi-commodity problem by mapping each trunk as a commodity. However, in the multi-commodity model, the resources or capacity used by a unit of any commodity is the same. This condition is too restrictive for contemporary multi-rate broadband networks because a high bandwidth traffic trunk consumes more bandwidth than a trunk with low bandwidth requirement. The invention provides a method to modify the multi-commodity model so that the capacity utilized by different trunks does not have to be identical.

Abstract: This invention relates generally to a method for growing single-wall carbon nanotube (SWNT) from seed molecules. The supported or unsupported SWNT seed materials can be combined with a suitable growth catalyst by opening SWNT molecule ends and depositing a metal atom cluster. In one embodiment, a suspension of seed particles containing attached catalysts is injected into an evaporation zone to provide an entrained reactive nanoparticle. A carbonaceous feedstock gas is then introduced into the nanoparticle stream under conditions to grow single-wall carbon nanotubes. Recovery of the product produced can be done by filtration, centrifugation and the like.

Abstract: When resources are reported missing within a system they are logged in a system error log. Specifically, resources that are missing because they have been reassigned from one logical partition (LPAR) within the system to another LPAR are tagged. When diagnostics are run to resolve missing resources, the resource reconfiguration database is queried for all resources that were assigned to LPARs and now are reported as missing and a missing resource List is created. The system error log is searched for resources that are tagged as missing because of reassignment. Any tagged resource and associated child resources of the tagged resource are removed from the missing resource List thereby updating the List. Normal missing resource resolution procedures are run against the updated missing resource List.

Abstract: A method for detecting sequential processing effects on integrated circuits to be manufactured in a manufacturing process, includes: determining a first random sequence for a plurality of wafers; performing a first process step on the plurality of wafers by a first process tool in accordance with the first random sequence; determining a second random sequence for the plurality of wafers; and performing a second process step on the plurality of wafers by a second process tool in accordance with the second random sequence. The method performs randomization of wafer processing sequences at the process tool itself. By performing randomization of wafer processing sequences at the process tool, the need for separate wafer handlers is eliminated, resulting in significant cost reduction, clean-room space savings, improved yield, improved manufacturing cycle time, and improved signal-detection capabilities.

Abstract: A method and system for calculating a branch target address. Upon fetching a branch instruction from memory, the n?1 lower order bits of the branch target address may be pre-calculated and stored in the branch instruction prior to storing the branch instruction in the instruction cache. Upon retrieving the branch instruction from the instruction cache, the upper order bits of the branch target address may be recovered using the sign bit and the carry bit stored in the branch instruction. The sign bit and the carry bit may be used to select one of three possible upper-order bit value combinations of the branch target address. The selected upper-order bit value combination may then be appended to the n?1 lower order bits of the branch target address to form the complete branch target address.

Abstract: An interactive voice response system which statistically analyses word usage in speech recognition results to select prompts for use in the interaction. A received voice signal is converted to text and calculating factors such as context and task word ratios and word rate. These factors are used to make dialogue decisions as to the whether to use expert, intermediate, or novice prompts depending on whether the factor falls below, inside or above a threshold range.

Abstract: Packetized voice, video, and data traffic (data frames) are received in a communication traffic sorter. The data frames have a dispatch priority corresponding to their transmission characteristics (flow) and a quality of service parameters. The communication traffic sorter analyzes information in data packets within each data frame and determines an optimum flow for the data frames. A data frame is assigned to a selected queue based on an analysis of the information in its data packets. A data frame may also be assigned to a queue based on a prior analysis of a data frame with like transmission characteristics. Results of analysis are stored and indexed to facilitate processing of subsequent data frames. The network access sorter has circuits to un-pack and re-pack the data frame, when called for, to allow user transmitted data to be processed to create a modified data frame.

Abstract: A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

Abstract: An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.

Abstract: A telephone and voice mail (voice processing) system, which is implemented using only a single processing means for controlling operations of both the telephone system and the voice mail system, permits a caller, which has been placed on-hold, to request and be connected to another destination, such as another telephone extension in the system. Such a process may be performed by a recognition of digits dialed by the caller placed on-hold and then making a connection of the call to the requested extension number associated with the digits dialed.

Abstract: This invention relates generally to forming arrays of single-wall carbon nanotubes (SWNT) and compositions thereof. In one embodiment, the present invention involves forming an array from more than one separately prepared molecular arrays or templates to prepare a composite structure. The multiple arrays can be the same or different with respect to the SWNT type or geometric arrangement in the array.

Abstract: This invention relates generally to a single-wall carbon nanotube (SWNT) purification process and more particularly to a purification process that comprises heating the SWNT-containing felt under oxidizing conditions to remove the amorphous carbon deposits and other contaminating materials. In a preferred mode of this purification procedure, the felt is heated in an aqueous solution of an inorganic oxidant, such as nitric acid, a mixture of hydrogen peroxide and sulfuric acid, or a potassium permanganate. Preferably, SWNT-containing felts are refluxed in an aqueous solution of an oxidizing acid at a concentration high enough to etch away amorphous carbon deposits within a practical time frame, but not so high that the single-wall carbon nanotube material will be etched to a significant degree. When material having a high proportion of SWNT is purified, the preparation produced will be enriched in single-wall nanotubes, so that the SWNT are substantially free of other material.

Abstract: A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.

Abstract: A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each group of cells, each cell may be coupled to a ground path and to a power path. A device, e.g., n-type transistor, p-type transistor, may be coupled to either the ground or power path in each group of cells thereby permitting the passing of the sub-threshold leakage from those cells in that group through the device. Consequently, the sub-threshold leakage in the memory array may be reduced.

Abstract: A method, system and computer program product for efficiently handling client requests in a server farm. A server in the server farm may comprise a hardfile constrained to activate a limited number of logical partitions. The hardfile may store a partition table that defines the logical partitions activated. An image may refer to a collection of the limited number of logical partitions. Each image may be associated with a web site. Hence, the server may host a web site associated with the image currently active. The server may further store an image definition table storing a listing of images. An image associated with a different web site than the web site hosted may be selected. The logical partitions of the image selected may substitute the logical partitions defined in the partition table. Consequently, the server hosts a different web site without copying the old image or installing the new image.

Abstract: A data transmission system for exchanging packetized data between any IP host selected from a cluster of IP hosts, each host having at least an IP layer, a network layer, and a plurality of workstations coupled by an intermediary of an IP network. The IP hosts are coupled to the IP network via a layer 2 network such as a LAN interfacing the IP network by a set of routers and a network dispatcher that receives all incoming data flow and dispatches the data to the cluster of hosts. The data transmission system comprises at least a monitoring device included in the cluster of hosts where the monitoring device is operable to monitor the availability of candidate routers selected from the set of possible routers. The monitoring device also is operable for broadcasting router availability information to each host in the cluster of hosts via the network dispatcher.

Abstract: A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.