Abstract: A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.

Abstract: A method and system for performing a two-step read on a count register as an atomic read in a home network is disclosed. The count register has a lower half and an upper half, and is incremented in response to an increment signal and is read in response to a read signal. The method and system include reading the lower half of the count register and storing the upper half of the count register in a shadow register in response to detecting the increment signal. The shadow register is then read in order to obtain the value of the upper half of the count register, thereby avoiding reading an incorrect result from the register.

Abstract: A method and apparatus for identifying individual semiconductor die that originate from a semiconductor substrate containing a plurality of die is disclosed. Aspects of the invention include physically associating a respective die ID with at least a portion of individual die on the wafer, and storing the die ID and wafer fabrication information in a database. During subsequent testing of the die, the die ID is used to retrieve the wafer fabrication information from the database, thereby aiding a determination as to a cause of a failure of the die.

Abstract: A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring it is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.

Abstract: Disclosed is a method and system of selecting a server from a plurality of servers for accessing Systems Network Architecture (SNA) applications from a client in an Internet Protocol (IP) network. The method comprises the steps of measuring using measurement probes from one or a plurality of measurement systems distributed in the IP network, performance and availability of each server for accessing one or a plurality of SNA applications; transferring in a single system within the IP network said performance and response time measurements; selecting in said single system an appropriate server for accessing a particular SNA application using said performance and availability measurements.

Abstract: This invention is directed to making chemical derivatives of carbon nanotubes and to uses for the derivatized nanotubes, including making arrays as a basis for synthesis of carbon fibers. In one embodiment, this invention also provides a method for preparing single wall carbon nanotubes having substituents attached to the side wall of the nanotube by reacting single wall carbon nanotubes with fluorine gas and recovering fluorine derivatized carbon nanotubes, then reacting fluorine derivatized carbon nanotubes with a nucleophile. Some of the fluorine substituents are replaced by nucleophilic substitution. If desired, the remaining fluorine can be completely or partially eliminated to produce single wall carbon nanotubes having substituents attached to the side wall of the nanotube. The substituents will, of course, be dependent on the nucleophile, and preferred nucleophiles include alkyl lithium species such as methyl lithium.

Abstract: The present invention relates to dynamic Client configuration and more particularly to a system and a method for automatically configuring a Client to access each desired SNA Application through an appropriate Server. A configuration feature (also called Automatic Server Configuration option) in a Client automatically retrieves a configuration code (also called Autoserver code, in order to configure the Client to access desired SNA Applications through appropriate Servers. A CGI (Common Gateway Interface, program on an Autoserver URL (Universal Resource Locator) system dynamically creates an Autoserver code (also called TN client configuration code). The Autoserver code is used by the Client to associate to each desired SNA Application an appropriate Server. The automatic configuration of the Client allows the user to directly access an SNA Application without having first to connect to an Intermediate Selection Application and Selection Screen.

Abstract: This invention relates generally to a method for producing single-wall carbon nanotube (SWNT) catalyst supports and compositions thereof. In one embodiment, SWNTs or SWNT structures can be employed as the support material. A transition metal catalyst is added to the SWNT. In a preferred embodiment, the catalyst metal cluster is deposited on the open nanotube end by a docking process that insures optimum location for the subsequent growth reaction. The metal atoms may be subjected to reductive conditions.

Abstract: A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. Tracing of the program flow includes tracing instructions both before and after a trace triggering event. The implementation of periodic synchronizing events enables the tracing of instructions occurring before and after a triggering event, and then providing the trace information externally from the processor.

Abstract: A method, computer program product and system for detecting a first-hop dead gateway. In one embodiment, a method comprises the step of sending a TCP packet of data from an application of a sender host to a receiver host through a first gateway, where the first gateway is a first-hop away from the sender host. The method further comprises the step of TCP failing to receive an acknowledgment of received data from the receiver host. The method further comprises the step of deleting an ARP entry associated with the first gateway in the sender host. The method further comprises the step of establishing a new communication using the first gateway by the application or new application of the sender host. The method further comprises the step of sending an ARP request to the first gateway by the sender host.

Abstract: A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.

Abstract: A parallel decompression system and method which decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. A token may represent one or more compressed symbols or one uncompressed symbol. The parallel decompression engine may also include preliminary select generation logic for generating a plurality of preliminary selects in parallel. A preliminary select may point to an uncompressed symbol in the history window, an uncompressed symbol from a token in the current decompression cycle, or a symbol being decompressed in the current decompression cycle.

Abstract: A method for securing and processing sparse access control list (ACL) data in a relational database used as a backing store for a hierarchical-based directory service. The sparse ACL data is secured in a plurality of tables. An owner table stores data objects with explicitly set ACLs. A propagation table stores data on whether individual ACLs are inherited by descendant objects. A permissions table stores data regarding permissions which a user may perform on an object. A source table stores data for a set of ancestor objects having respective ACLs for each of a set of descendant objects. Preferably, the tables are stored in the relational database together with the objects. For a given object, data in the tables is used to determine the given object's entry owner and ACL. The inventive technique has particular applicability in a Lightweight Directory Access Protocol (LDAP) directory service having a relational database as a backing store.

Abstract: A method, network system and computer program product for establishing a server node in a virtual private network with a single tunnel definition and a single security policy for a plurality of tunnels associated with a group name. In one embodiment, a method comprises the step of configuring a group database in the server node. The group database in the server node comprises the group name and a list of members associated with the group name. The method further comprises configuring a rules database in the server node. The rules database associates the group name with a particular security policy. The method further comprises configuring a tunnel definition database in the server node. In the tunnel definition database, the remote ID is defined as the group name. In another embodiment of the present invention, the list of members associated with the group name comprises a non-contiguous list of ID types.

Abstract: A branch prediction method includes the step of retrieving prediction values from a local branch history table and a global branch history table. A branch prediction operation is selectively performed using the value retrieved from the local branch history table when the value from the local branch history table falls within first predicted limits. A branch prediction operation is selectively performed using the value retrieved from the global branch history table when the value from the global branch history falls within a second predetermined limit.

Abstract: A carbon film having an area of insulating material surrounded by an area of conducing material, and an area of material between the area of insulating material and the area of conducting material having a graded dielectric constant which varies from high to low from the area of insulating material to the area of conducting material.

Abstract: A field emission cold cathode utilizes a film of carbon flake field emitters deposited thereon. The carbon flakes may exhibit rolled edges, but are still sufficient to provide improved field emission characteristics. A cold cathode using such carbon flake field emitters can be utilized to produce afield emission flat panel display, which can be implemented for use with a computer system.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of parallel data compression and/or parallel data decompression engines designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. The plurality of compression/decompression engines may each implement a parallel lossless data compression/decompression algorithm. The codec system may split incoming uncompressed or compressed data up among the plurality of compression/decompression engines. Each of the plurality of compression/decompression engines may compress or decompress a particular part of the data. The codec system may then merge the portions of compressed or uncompressed data output from the plurality of compression/decompression engines. The codec system may implement a method for performing parallel data compression and/or decompression designed to process stream data at more than a single byte or symbol at one time.

Abstract: A method and system for accessing a shared memory in a deterministic schedule. In one embodiment, a system comprises a plurality of processing elements and a system I/O controller where each processing element and system I/O controller comprises a DMA controller. The system further comprises a shared memory coupled to each of the plurality of processing elements where the shared memory comprises a master controller. The master controller may then issue tokens to DMA controllers to grant the right for the associated processing elements and system I/O controller to access the shared memory at deterministic points in time. Each token issued by the master controller grants access to the shared memory for a particular duration of time at a unique deterministic point in time. A processing element or system I/O controller may access the shared memory upon the associated DMA controller relinquishing to the master controller the token that grants the right to access the shared memory at that particular time.

Abstract: A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113. A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108, a direct memory access engine 105 for controlling the exchange of information through memory interface 108, and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101, a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.