Abstract: A method and system for allowing a processor or I/O master to address more system memory than physically exists are described. A Compressed Memory Management Unit (CMMU) may keep least recently used pages compressed, and most recently and/or frequently used pages uncompressed in physical memory. The CMMU translates system addresses into physical addresses, and may manage the compression and/or decompression of data at the physical addresses as required. The CMMU may provide data to be compressed or decompressed to a compression/decompression engine. In some embodiments, the data to be compressed or decompressed may be provided to a plurality of compression/decompression engines that may be configured to operate in parallel. The CMMU may pass the resulting physical address to the system memory controller to access the physical memory. A CMMU may be integrated in a processor, a system memory controller or elsewhere within the system.

Abstract: CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where circuitry does not have power supply gating. Each output that couples signals from one logic circuit domain to another logic circuit is interfaced with a C_driver and a S_keeper which automatically assure that the output state is held when circuitry is power-gated put to reduce leakage power. The S_keeper and C_driver have low leakage circuits that maintain signal states and are not used for high speed operation.

Abstract: A circuit for implementing a registration-free, contiguous conductive plane. A circuit may include a plurality of conductive structures in a first plane. The circuit may further include a contiguous conductive equipotential surface in a second plane parallel to the first plane. The circuit may further include activation means configured to adjust an electric field between the first and second planes thereby activating one or more structures in the first plane by increasing a potential difference between the first and second planes to a threshold level deemed to constitute an active state. The circuit may further include deactivation means configured to adjust the electric field between the first and second planes thereby deactivating one or more structures in the first plane by decreasing the potential difference between the first and second planes below a threshold level deemed to constitute a deactivation state.

Abstract: A computer system preferably a mobile client computer, optimizes data handling and display through the use of predictive widgets. A predictive widget uses a predictive list of possible entries into a defined field of a form, as in a form filling application, to provide one or both of a predictive default entry for a field or a predictive fill once a user has started an entry into the field.

Abstract: This invention relates generally to a method for producing single-wall carbon nanotube (SWNT) catalyst supports and compositions thereof. In one embodiment, SWNTs or SWNT structures can be employed as the support material. A transition metal catalyst is added to the SWNT. In a preferred embodiment, the catalyst metal cluster is deposited on the open nanotube end by a docking process that insures optimum location for the subsequent growth reaction. The metal atoms may be subjected to reductive conditions.

Abstract: The present invention is directed toward cathodes and cathode materials comprising carbon nanotubes (CNTs) and particles. The present invention is also directed toward field emission devices comprising a cathode of the present invention, as well as methods for making these cathodes. In some embodiments, the cathode of the present invention is used in a field emission display. The invention also comprises a method of depositing a layer of CNTs and particles onto a substrate to form a cathode of the present invention, as well as a method of controlling the density of CNTs used in this mixed layer in an effort to optimize the field emission properties of the resulting layer for field emission display applications.

Abstract: A massively distributed processing system and associated methods are disclosed that provide a processing architecture for utilizing a multitude of widely distributed devices to process distributed project workloads. To provide the processing infrastructure, a modular client agent program, which may include a system component and a separate project component, operates on the distributed devices to process workloads. For different projects, different project components may be provided to run on the base system component. In addition, a device capabilities database and an incentive database can be used by the server system to facilitate operations and encourage participation by client systems. Other databases may also be utilized to enhance system operations and functionality.

Abstract: A fluorescent trace material is provided within at least a portion of an electrical contact or interrupter assembly component, or a cavity defined therein. At least a portion of the fluorescent trace material is exposed or released from the electrical contact or interrupter assembly component, indicating a degree of component wear.

Abstract: A system for controlling a dynamic pressure transient in a well during operations to provide fluid communication between the wellbore and adjacent formation. A method includes determining the characteristics of an adjacent formation, selecting a perforating tool for increasing fluid communication, determining a dynamic pressure transient to enhance the quality of the fluid communication and prevent damage, selecting a wellbore fluid to achieve the desired pressure transient, and performing the fluid communication process based on the selected parameters.

Abstract: Electronic billboards, which may be indoor or outdoor are located in various geographical areas. Associated with each billboard is a web address. A client desiring to display information, such as an advertisement, on any selected electronic billboard can upload the information over the Internet to the server implementing the billboard website. The client can select the time and duration for the information to be displayed, and can even purchase the display time using a credit card or through the use of some other type of account.

Abstract: A method, system and computer program product for eliminating memory corruption when performing multi-threaded tree operations. A network processor may receive a command to perform a tree operation on a tree on one or more of multiple threads. Upon performing the requested tree operation, the network processor may lock one or more resources during a portion of the execution of the requested tree operation using one or more semaphores. A semaphore may refer to a flag used to indicate whether to “lock” or make available the resource associated with the semaphore. Locking may refer to preventing the resource from being available to other threads. Hence, by locking one or more resources during a portion of the tree operation, memory corruption may be eliminated in a multiple thread system while preventing these resources from being used by other threads for a minimal amount of time.

Abstract: A method for cutting single-wall carbon nanotubes involves partially fluorinating single-wall carbon nanotubes and pyrolyzing the partially fluorinated nanotubes in an inert atmosphere or vacuum up to about 1000° C. The nanotubes are optionally purified before cutting. The partial fluorination involves fluorinating the nanotubes to a carbon-fluorine stoichiometry of CFx, where x is up to about 0.3. The invention also relates to the derivatization of fluorinated and cut single-wall carbon nanotubes. The single-wall carbon nanotubes can be cut to any length depending on the fluorination and pyrolysis conditions. Short nanotubes are useful in various applications, such as field emitters for flat panel displays and as “seeds” for further nanotube growth.

Abstract: A method and apparatus for calibrating failures in semiconductor memory devices due to contact mask misalignment includes: providing a plurality of semiconductor memory devices on a die; providing a contact mask with a plurality of known offsets; creating a plurality of contacts on the die using the contact mask; determining which devices on the die fail; and creating a pass/fail map for the devices. The pass/fail map can be used to determine the range of allowed misalignment and the amount of misalignment, providing a better understanding of how contact mask misalignment affects the yield and reliability of the memory devices. The pass/fail map may also be used for comparison with a pass/fail map created after the arrays have been subjected to a known stress.

Abstract: A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.

Abstract: A method and system for identifying and configuring device-enhanced memory modules at system startup is described. A driver is described that performs a wakeup procedure at startup to identify installed device-enhanced memory modules, detect memory implementations such as interleaving and striping on memory modules, detect error detection and correction (ECC) implementations, and to configure the identified device-enhanced memory modules to use the detected implementations. The method may include several phases including, but not limited to, a start block phase, an ECC configuration phase, an ECC check phase, an interleave detect and configuration phase, a buffer check phase, and a final configuration phase. One or more of the phases may be performed at system startup and/or during normal system operation. Methods for shutting down and providing a sleep mode for device-enhanced memory modules are also described.

Abstract: A system and method for exposing and/or milling a copper metallization layer disposed in dielectric that may have an overlying polyimide layer preferably by use of a FIB machine system used for exposing/milling aluminum metallization layers is disclosed. The method includes using a gas assisted (GAS) system for exposing a portion of a copper metal trace disposed in a dielectric and includes the step of removing a portion of the dielectric overlying the portion of the metal trace using the GAS system activated with a dielectric selective chemical that does not have a significant spontaneous (non ion-beam induced) reaction with the metal trace. The system includes a focused ion beam (FIB) machine for exposing/milling a portion of a metal trace disposed in a dielectric substrate wherein the metal trace is copper.

Abstract: A constant ON-time controller for a buck converter utilizes dual symmetrical ramps. The ramps may be generated artificially or by sensing the voltage across a sense resistor in the output. The ramp may also be generated by sensing the voltage across the “ON” resistance of the low side FET in the switching regulator. A modified output voltage has one of the ramps superimposed and a modified reference voltage has the other ramps superimposed. The modified output voltage and the modified reference voltage are compared to determine when to start the ON-time of the buck converter. The dual ramps reduce, noise susceptibility. The ON-time is stopped in response to charging a capacitor with the regulator input voltage. An offset may also be generated representing the difference between the average output voltage and the reference voltage. The offset is used to generate a modified reference to compensate for the offset.