Patents Represented by Attorney Winstead, Sechrest & Minick, P.C.
  • Patent number: 7000047
    Abstract: A method and multithreaded processor for handling livelocks in a simultaneous multithreaded processor. A number of instructions for a thread in a queue may be counted. A counter in the queue may be incremented if the number of instructions for the thread in the queue in a previous clock cycle is equal to the number of instructions for the thread in the queue in a current clock cycle. If the value of the counter equals a threshold value, then a livelock condition may be detected. Further, if the value of the counter equals a threshold value, a recovery action may be activated to handle the livelock condition detected. The recovery action may include blocking the instructions associated with a thread causing the livelock condition from being executed thereby ensuring that the locked thread makes forward progress.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Dung Quoc Nguyen, Raymond Cheung Yeung
  • Patent number: 7000233
    Abstract: An SMT system has a single thread mode and an SMT mode. Instructions are alternately selected from two threads every clock cycle and loaded into the IFAR in a three cycle pipeline of the IFU. If a branch predicted taken instruction is detected in the branch prediction circuit in stage three of the pipeline, then in the single thread mode a calculated address from the branch prediction circuit is loaded into the IFAR on the next clock cycle. If the instruction in the branch prediction circuit detects a branch predicted taken in the SMT mode, then the selected instruction address is loaded into the IFAR on the first clock cycle following branch predicted taken detection. The calculated target address is fed back and loaded into the IFAR in the second clock cycle following branch predicted taken detection. Feedback delay effectively switches the pipeline from three stages to four stages.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: David Stephen Levitan, Balaram Sinharoy
  • Patent number: 7000096
    Abstract: A method of generating a Global History Vector includes the steps of determining if a selected group of instructions contains a branch instruction. A current Global History Vector is maintained in a shift register when the selected group does not contain a branch instruction. A first value is shifted into the shift register to generate a second vector if the selected group contains a branch instruction which is predicted to be a branch taken. A second value is shifted into the shift register to generate a second vector when the selected group contains a branch instruction and the selected group does not include a branch instruction predicted to be a branch taken.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventor: Balaram Sinharoy
  • Patent number: 6996124
    Abstract: The present invention provides a method for supporting sleep mode wake up in a home phone line network. The method includes: detecting a limited automatic repeat request (LARQ) header in a frame; stripping the LARQ header and a frame check sequence (FCS) in the frame; recalculating the FCS for the stripped frame; and adding the recalculated FCS to the stripped frame. The method strips the LARQ header from a HPNA frame before it is sent to an Ethernet controller. By stripping the LARQ header, the Ethernet controller will correctly find the set byte location for the wake pattern and attempts to match the bit pattern with the wake pattern. In this manner, sleep mode wake up is supported.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Peter Ka-Fai Chow
  • Patent number: 6995564
    Abstract: Aspects for locating chip-level defects through emission imaging of a semiconductor device are described. The aspects include providing a semiconductor device for inspection within an emission imaging system. Emission detection from a frontside and backside of the semiconductor device substantially simultaneously is then performed in the emission imaging system, wherein the emissions detected indicate potential defects within the semiconductor device.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Boon Y. Ang, Mehrdad Mahanpour, Mohammed Massoodi
  • Patent number: 6991946
    Abstract: The present inventive principles provide a method and system for performing backside voltage contrast on an SOI device. The SOI semiconductor device includes a bulk silicon, a box insulator residing on the bulk silicon and a silicon region on the box insulator. The SOI semiconductor device further includes a plurality of structures in the silicon region, the plurality of structures includes a conductive structure. The method and system include mechanical dimpling and chemical etching of the substrate to expose the box insulator. Optionally, a second chemical etch to remove at least a portion of the box insulator may be performed. A charged particle beam, such as energetic electrons from an SEM, for example, may be directed at the backside of the device, and emitted secondary electrons observed.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: January 31, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mehrdad Mahanpour, Mohammad Massodi, Caiwen Yuan
  • Patent number: 6993650
    Abstract: A method, computer program product and system for storing or updating authentications, e.g., passwords, in a boot code image, i.e., binary executable boot code, stored within a Read Only Memory (ROM), e.g., flash ROM, of a terminal from a remote central site. An authentication may be stored in the boot code image in a terminal from a central site by creating a file comprising a boot code image storing the authentication at the central site and then storing the created file in ROM in the terminal. The file may be downloaded from a server at the central site to the terminal. An authentication in the boot code image in a terminal may be updated remotely from a central site by updating the file associated with the boot code image, i.e., updating the authentication, at the central site and then downloading the updated file to the terminal.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: January 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: John David Landers, Jr., Robert Eugene Russell, Jr., David John Steiner
  • Patent number: 6986876
    Abstract: This invention relates generally to forming arrays of single-wall carbon nanotubes (SWNT). In one embodiment, the present invention involves forming a macroscopic molecular array of tubular carbon molecules, said method comprising the step of assembling subarrays of up to 106 single-wall carbon nanotubes into a composite array.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: January 17, 2006
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Daniel T. Colbert, Hongjie Dai, Jie Liu, Andrew G. Rinzler, Jason H. Hafner, Kenneth A. Smith, Ting Guo, Pavel Nikolaev, Andreas Thess
  • Patent number: 6985952
    Abstract: Cluster systems having central processor units (CPUs) with multiple processors (MPs) are configured as high density servers. Power density is managed within the cluster systems by assigning a utilization to persistent states and connections within the cluster systems. If a request to reduce overall power consumption within the cluster system is received, persistent states and connections are moved (migrated) within the multiple processors based on their utilization to balance power dissipation within the cluster systems. If persistent connections and states, that must be maintained have a low rate of reference, they may be maintained in processors that are set to a standby mode where memory states are maintained. In this way the requirement to maintain persistent connections and states does not interfere with an overall strategy of managing power within the cluster systems.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Bohrer, Elmootazbellah N. Elnozahy, Thomas W. Keller, Michael D. Kistler, Freeman L. Rawson, III
  • Patent number: 6980018
    Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: December 27, 2005
    Assignee: Internatiional Business Machines Corporation
    Inventors: Hung C. Ngo, Jente B. Kuang, Kevin J. Nowka
  • Patent number: 6979619
    Abstract: In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: December 27, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hao Fang, Yue-Song He, Mark S. Chang, Kent K. Chang
  • Patent number: 6979947
    Abstract: A field emission device includes a substrate in which a well has been formed. Carbon fibers with a high aspect ratio are deposited within the well, wherein the well is sufficiently deep so that axes of a large number of the carbon fibers are substantially coaxial with a long axis of the well. A conductive anode is positioned relative to the substrate so that an electric potential applied between the conductive anode and the substrate causes an emission of electrons from the carbon fibers towards the conductive anode.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: December 27, 2005
    Assignee: SI Diamond Technology, Inc.
    Inventors: Zvi Yaniv, Richard Lee Fink
  • Patent number: 6981128
    Abstract: In a system with multiple execution units, instructions are queued to allow efficient dispatching. One load/store unit (LSU) may have a store instruction pending to a real address and a second LSU may have a load instruction pending to the same real address. An SMT system has an atomic store quad word (SQW) instruction with a data path that is only double wide and the SQW requires two cycles to complete. The SMT system requires a method to prevent between collisions in a store reorder queue (SRQ) STQ. The real address of a load word (LW) one thread is compared to the real addresses in the SRQ of the second thread. If the SQW with a real address matching the real address of the LW has not committed both of its double words, then the LW of the second thread is rejected.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Eric J. Fluhr, Joaquin Hinojosa, Ronald N. Kalla, Bruce J. Ronchetti, Balaram Sinharoy
  • Patent number: 6979709
    Abstract: This invention relates generally to carbon fiber produced from single-wall carbon nanotube (SWNT) molecular arrays. In one embodiment, the present invention involves a macroscopic carbon fiber comprising at least 106 signal-wall carbon nanotubes in generally parallel orientation.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: December 27, 2005
    Assignee: William Marsh Rice University
    Inventors: Richard E. Smalley, Daniel T. Colbert, Hongjie Dai, Jie Liu, Andrew G. Rinzler, Jason H. Hafner, Kenneth A. Smith, Ting Guo, Pavel Nikolaev, Andreas Thess
  • Patent number: 6974995
    Abstract: A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: December 13, 2005
    Assignees: Advanced Micro Devices, Inc., Spansion LLC
    Inventors: Angela Hui, Shenqing Fang, Hiroyuki Kinoshita, Kelwin Ko, Wenmei Li, Yu Sun, Hiroyuki Ogawa, Chi Chang
  • Patent number: 6976157
    Abstract: Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of entries each for storing a prediction value and accessed by selected bits of a branch address. The fetch-based branch history table included a plurality of entries for storing a prediction value and accessed by a pointer generated from selected bits of the branch address and bits from a history register. The selector table includes a plurality of entries each for storing a selection bit and accessed by a pointer generated from selected bits from the branch address and bits from the history register, each selector bit is used for selecting between a prediction value accessed from the local history table and a prediction value accessed from the fetch-based history table.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventor: Balaram Sinharoy
  • Patent number: 6973970
    Abstract: A tool for making a cut inside a downhole tool, including a housing adapted to move in the downhole tool, a plurality of openings in a wall of the housing that provides a passage from inside the housing to an exterior of the housing, a plurality of cutters disposed in the housing that are adapted to protrude from the plurality of openings to the exterior of the housing, wherein the plurality of cutters provides 360 degree cutting regardless of the orientation of the tool, and an actuation mechanism adapted to force the plurality of cutters to protrude through the plurality of openings.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: December 13, 2005
    Assignee: Schlumberger Technology Corporation
    Inventors: Russell A. Johnston, Michael A. Dowling
  • Patent number: 6975134
    Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka
  • Patent number: 6975063
    Abstract: The present invention is directed towards metallized carbon nanotubes, methods for making metallized carbon nanotubes using an electroless plating technique, methods for dispensing metallized carbon nanotubes onto a substrate, and methods for aligning magnetically-active metallized carbon nanotubes. The present invention is also directed towards cold cathode field emitting materials comprising metallized carbon nanotubes, and methods of using metallized carbon nanotubes as cold cathode field emitters.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 13, 2005
    Assignee: SI Diamond Technology, Inc.
    Inventors: Dongsheng Mao, Zvi Yaniv, Richard Lee Fink
  • Patent number: 6973503
    Abstract: A method, system and computer program product for preventing at least in part overloading of a control processor. A network device may comprise at least one network processor and at least one control processor. The control processor may be configured to process slow path packets that are redirected from a network processor to the control processor. The control processor may configure control blocks to determine if the bandwidth for the control processor will be exceeded by the network processor transferring another slow path packet to the control processor. If the control block determines that transmitting the slow path packet would exceed the processing capacity of the control processor, then the control block may generate a result indicating for the network processor to discard the received packet. By discarding packets that exceed the processing capacity of the control processor, overloading of the control processor may at least in part be prevented.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Max Robert Povse, Natarajan Vaidhyanathan, Colin Beaton Verrilli