Abstract: When activities are operated in parallel, and there is only one status display, an ordered list is implemented with three methods of access: insertion at the top, removal from anywhere, and read of the top item. Items kept on this list are the status codes or words for the activities that are currently in progress. When a new activity begins, its status code or word is inserted at the top of the list. Whenever an activity completes, its code or word is removed from the list regardless of its location in the list, and in such a way as to preserve the order of the remaining entries in the list. Whenever the top entry in the list changes (whether through an insertion or removal), the single status display is updated to show the new top value.

Abstract: The invention concerns a method and apparatus for indicating a parameter of a transmitted fluid. One embodiment of the invention comprises a fluid source operatively coupled to a conduit for transmitting a fluid from the fluid source. In addition, a sensor detects a parameter of the fluid, such as the percent oxygen content of the fluid. In response to the sensor detecting the parameter of the fluid, an indicator illuminates a portion of the conduit if a predetermined condition, such as a minimum percent oxygen content of the fluid, is satisfied.

Abstract: The present invention relates to an all gas-phase process for the purification of single-wall carbon nanotubes and the purified single-wall carbon nanotube material. Known methods of single-wall carbon nanotube production result in a single-wall carbon nanotube product that contains single-wall carbon nanotubes in addition to impurities including residual metal catalyst particles and amounts of small amorphous carbon sheets that surround the catalyst particles and appear on the sides of the single-wall carbon nanotubes and “ropes” of single-wall carbon nanotubes. The purification process removes the extraneous carbon as well as metal-containing residual catalyst particles. The process comprises oxidation of the single-wall carbon nanotube material, reduction and reaction of a halogen-containing gas with the metal-containing species. The oxidation step may be done dry or in the presence of water vapor.

Abstract: A single rename register array is used in an SMT processor. Two bits are added to each register address of the rename register array, one for bit for thread zero (CTB0) and one bit for thread one (CTB1). The CTB bits are all set to a logic value on power on or start-up. A control instruction (CI) that sets control bits used by other instructions is assigned a register in the rename register array having an address designated as pointer (PTR) address. When a control instruction with an assigned entry with PTR address M completes, then the CTB bit at the PTR address M is flipped to its opposite logic state; likewise, its Valid bit is set to a “not” Valid state. The self resetting CTB bit is used to determine whether an issued instruction sources a register in the rename register array or a corresponding architected register.

Abstract: A circuit for implementing a registration-free, contiguous conductive plane. A circuit may include a plurality of conductive structures in a first plane. The circuit may further include a contiguous conductive equipotential surface in a second plane parallel to the first plane. The circuit may further include activation means configured to adjust an electric field between the first and second planes thereby activating one or more structures in the first plane by increasing a potential difference between the first and second planes to a threshold level deemed to constitute an active state. The circuit may further include deactivation means configured to adjust the electric field between the first and second planes thereby deactivating one or more structures in the first plane by decreasing the potential difference between the first and second planes below a threshold level deemed to constitute a deactivated state.

Abstract: An system IC is partitioned into test ICs that have a sub-set of the functionality of the system IC. The test ICs have chip I/O pads conforming to a sub-set arrangement of the system IC chip I/O pads. A packaging module is designed to accept means for attaching and fanning-out the system IC chip I/O pads to lower density packaging I/O pads. A test IC is electrically coupled to the packaging module and tested by programming signals and power to the signal and power pads on the module packaging I/O pads corresponding to chip I/O pads for the test IC. Functionality of the system IC may be partitioned into a plurality of test ICs, each with chip I/O pads that conform to an individual sub-set of the system IC I/Os. Two or more of the plurality of test ICs are coupled to the system IC packaging module for testing.

Abstract: A mechanism for caching Web services requests and responses, including testing an incoming request against the cached requests and associated responses is provided. The requests are selectively tested against the cached data in accordance with a set of policies. If a request selected hits in the cache, the response is served up from the cache. Otherwise, the request is passed to the corresponding Web-services server/application. Additionally, a set of predetermined cache specifications for generating request identifiers may be provided. The identifier specification may be autonomically adjusted by determining cache hit/cache miss ratios over the set of identifier specifications and over a set of sample requests. The set of specifications may then be sorted to reflect the performance of the respective cache specification algorithms for the current mix of requests.

Abstract: A method and system for recovering a global history vector. In the event of a non-branch flush, a tag may be received by a queue configured to store information about branch instructions. The queue may read a copy of the global history vector from an entry indexed by the tag. This copy may be inserted in a global history vector mechanism (“GHV mechanism”) configured to manage the global history vector. If the flush operation is a flush to a group of instructions that contains no branch instructions and the tag does not equal the next-to-write pointer in the queue, then the queue may transmit a command to the GHV mechanism to enter a mode where the GHV mechanism does not update the global history vector until the next branch instruction is fetched.

Abstract: A method for managing workloads and associated distributed processing system are disclosed that identify the capabilities of distributed devices connected together through a wide variety of communication systems and networks and utilize those capabilities to organize, manage and distribute project workloads to the distributed devices.

Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.

Abstract: The present invention provides a method for providing data sharing and filed distribution in a distributed processing system. The distributed processing system identifies and utilizes the capabilities of distributed devices connected together through a wide variety of communication systems and networks and utilizes those capabilities to organize, manage and distribute project workloads to the distributed devices.

Abstract: At system power on, a query is sent from a PCI or host-based controller to an attached codec for the vendor specific identification code associated with that codec. The PCI/host controller then sets its PCI vendor and subvendor ID's to match the specific system comprised of the controller and codec devices. That vendor specific identification code is then utilized within the PCI enumeration process to search for the specific modem driver associated with that codec.

Abstract: An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued each cycle, and an instruction should be selectable for issuing as soon as its source operands are available. An instruction in the issue queue having source operands depending on other, target, instructions to determine their value are signaled to the target instruction by a link mask in the queue entry corresponding to the target instruction. A bit in the link mask identifies the queue entry corresponding to the dependent instruction. When the target instruction issues to the execution unit, a bit is set in a predetermined portion of the queue entry containing the dependent instruction. The portion of the queue entry is associated with the source operand depending on the issuing instruction.

Abstract: A substantially rigid card having a first side and an opposing second side, a first connector end adapted to mate with a first expansion connector on a circuit board and a second connector end adapted to mate with a second expansion connector on the board. A first peripheral card connector is connected to the first side and electrically connected to the first connector end, wherein the first connector is of a first form factor and adapted to mate with a first peripheral card. A second peripheral card connector is connected to the second side and electrically connected to the second connector end, wherein the second connector is of a second form factor different from the first form factor and matable with a second peripheral card.

Abstract: The invention relates to a process for sorting and separating a mixture of (n, m) type single-wall carbon nanotubes according to (n, m) type. A mixture of (n, m) type single-wall carbon nanotubes is suspended such that the single-wall carbon nanotubes are individually dispersed. The nanotube suspension can be done in a surfactant-water solution and the surfactant surrounding the nanotubes keeps the nanotube isolated and from aggregating with other nanotubes. The nanotube suspension is acidified to protonate a fraction of the nanotubes. An electric field is applied and the protonated nanotubes migrate in the electric fields at different rates dependent on their (n, m) type. Fractions of nanotubes are collected at different fractionation times. The process of protonation, applying an electric field, and fractionation is repeated at increasingly higher pH to separated the (n, m) nanotube mixture into individual (n, m) nanotube fractions.

Abstract: This invention provides a method of making single-wall carbon nanotubes by laser vaporizing a mixture of carbon and one or more Group VIII transition metals. Single-wall carbon nanotubes preferentially form in the vapor and the one or more Group VIII transition metals catalyzed growth of the single-wall carbon nanotubes. In one embodiment of the invention, one or more single-wall carbon nanotubes are fixed in a high temperature zone so that the one or more Group VIII transition metals catalyze further growth of the single-wall carbon nanotube that is maintained in the high temperature zone. In another embodiment, two separate laser pulses are utilized with the second pulse timed to be absorbed by the vapor created by the first pulse.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing etching of a substrate and then depositing the film. The etching step creates nucleation sites on the substrate for the film deposition process. With this process patterning of the emitting film is avoided. A field emitter device can be manufactured with such a film.

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

Abstract: This invention relates generally to forming an array of single-wall carbon nanotubes (SWNT). In one embodiment, a macroscopic molecular array is provided comprising at least about 106 single-wall carbon nanotubes in generally parallel orientation and having substantially similar lengths in the range of from about 5 to about 500 nanometers.