Abstract: A clock monitor circuit which is frequency-independent. The crystal terminals on a circuit being monitored for activity may be considered as an inverter combined with a phase delay. The innovative circuit has clock-output and clock-input terminals which are connected to the clock terminals on the circuit being monitored. When a rising edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be high. Similarly, when a falling edge appears on the clock-output terminal, the clock-input line is sampled: if the circuit being monitored is properly active, the level on the clock-input line will be low. Whenever a low level is detected on a rising edge, or a high level on a falling edge, a counter chain will start counting down. The counter chain will be reset only when a high level is detected on a rising edge AND a low level is detected on the next falling edge.

Abstract: An adjunct chip, usable as a peripheral to a microprocessor, which detects power failure, and which puts the microprocessor into a known state upon power down. In order to reliably and stably put the microprocessor into a known state, several clocks are generated after the reset signal. However, since the power supply is falling, it is possible that the crystal-controlled oscillator may already have become unreliable. Therefore, a simple logic circuit (a ring oscillator, in the presently preferred embodiment) is used to generate the needed additional clocks at power-down. The switch from crystal-controlled oscillator to ring oscillator is stabilized by using a latched multiplexer to switch between the two oscillator inputs. The latch adds hysteresis to the switching characteristic, avoiding any problems of switching jitter.

Abstract: A very compact package for an electronic data module, which includes battery-backed memory. A two-part metal container is used, which has two shallow concave pieces which fit together. The integrated circuit (in a low-height package, such as a flat-pack or SOIC) is mounted on a very small flexible printed circuit board, which fits inside the container. Laterally spaced from the integrated circuit, on the other end of the small flexible board, the board end is sandwiched between a battery and a piece of elastic conductive material (such as conductive plastic foam). Thus, the battery is connected between one face of the container and a power conductor on the board. The piece of elastic conductive material makes contact between a data trace on the board and the other face of the container. Another trace on the board makes contact directly to the container face on which the battery's ground terminal is connected.

Abstract: A condenser in which the condenser tubes can be accessed for endoscopic examination in situ, without taking any part of the condenser off-line (except the specific tube being examined). The condenser's outlet water box has one or more inspection ports in its endwall, and a hollow rigid probe can be inserted through the outlet water box to dock with the end of a tube in the condenser. A flexible endoscopic probe can then be inserted through the rigid probe, to inspect the interior of the tube thus accessed. The rigid probe can also be used to isolate the flow of a single tube, if desired.

Abstract: A condenser structure wherein both ends of at least one tube, which is physically located among the other (numerous) tubes of the condenser's tube bundles, is not connected to the inlet water box nor to the outlet water box; instead, this tube is provided with separate inlet and outlet connections. The separate inlet connection is preferably provided with a separately-controlled admixture of water treatment chemicals. Also disclosed is an innovative method of operating a steam condenser. One or more tubes, which are physically located among the other (numerous) tubes of the condenser, are isolated to provide a real-time test loop. The tube thus isolated is chosen to be among the tubes with the highest heat load, so that this tube provides a worst-case proxy for scaling in the other condenser tubes. The isolated tube is frequently inspected for scaling (e.g.

Abstract: A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor.One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus.

Abstract: A low power timekeeping system utilizes a state machine to first read seconds stored in a RAM and update seconds and then determine if the minutes requires updating. If the minutes do not require updating then the sequencer stops operation until the next update cycle. Similarly, the minutes, hours, days of the week, date of the month, month, and year are updated only as needed in each update cycle thereby lowering the power requirement needed by the timekeeping system.

Abstract: An integrated circuit which includes switching logic to select its negative power supply voltage from the more negative of two signals (preferably ground and an input signal). Special MOS clamp diodes are used to prevent sharp transients from collapsing the voltage drop of the internal power supply lines (and so disabling the chip).

Abstract: A method of performing an integral transform operation (such as a Fast Fourier Transform), wherein the underlying algorithm is partitioned to provide an efficient sequence of data operations. Preferably the address calculations are performed separately from the data calculations, and the algorithm is partitioned so that the microcode sequence for all but the last few data calculations is constant. Thus, the bandwidth at the interface to the numeric processor is conserved, and control storage in the numeric processor is also efficiently conserved. Moreover, the preferred partition for performing Fast Fourier Transform manipulates data in reasonably large subsets (e.g. 8 floating-point words at a time). This turns out to use less data bandwidth than would be required using smaller data subsets.

Abstract: A DRAM controller which can be directly connected, without any automatic or selected reconfiguration, to DRAMs of various sizes. The externally-received address bits are remapped, so that the most significant two bits of the externally-received address bits are remapped onto the most significant bit of a row address and the most significant bit of a column address. This controller also provides selectable refresh periods.

Abstract: A RAM-based FIFO which provides self-timing of the data outputs in read mode. When the data output is not valid, the data output drivers are in a high-impedance condition. Therefore, FIFOs using this RAM-based architecture can readily be combined to provide a wider or deeper FIFO, without introducing any additional delay whatsoever. Small differential delays are preferably introduced in the activation of the output buffers, to avoid noise on power supply lines.

Abstract: A system which can provide short-range wireless data communication between a base station and a portable low-power module. Each portable module has an identification field by which it can be addressed separately. The identification field (which is 64 bits long in the presently preferred embodiment) can be parallel polled: By commanding all modules within range to respond, the base station can see the 64-bit identification fields combined in what is almost a "wired-OR" fashion. That is, if any one of the portable modules within range is pulsing (reporting a "1" bit) in a given time window, the base station will see a pulse; the base station will see the absence of a pulse only if all of the modules within range are reporting a "0" bit (not pulsing). This can be used, for example, to implement combinatorial logic functions on all (or some subfields of) the 64-bit identification field.

Abstract: A wand which provides rapid contact to a two-terminal electronic token data module. The wand includes one contact which will make contact to the periphery of an electronic token which the wand is pressed against, and one contact which will make contact to the center of the token. Preferably the wand includes a base portion which is shaped to be worn on the second joint of a user's finger. This wand can be used for very rapid manual contacting of electronic tokens in various physical positions. This can be very advantageous in a variety of data collection/updating applications such as retail checkout, or tracking work-in-progress in a computer-assisted-manufacturing environment.

Abstract: An integrated circuit which uses an unusual comparator design, which is not fully complementary but which has an extended common mode range, to control switching of one pole of the output driver (e.g. the lower pole) between an internal voltage (e.g. ground voltage) and a current extracted from an incoming signal.

Abstract: A system and method for monitoring conditions in a fluid medium. A stream of the fluid medium is flowed through a fluid container which is electrically configured as a transmission line segment and which is electrically connected to load to UHF or microwave oscillator. The oscillator is not isolated from the load, and is operated free-running, at a starting frequency which is chosen to provide a particularly strong shift in permittivity of the fluid medium, as the chemical reaction progresses. Preferably the frequency and insertion loss of the oscillator are monitored, to gauge the progress of the reaction.

Abstract: A bidirectional voltage to current converter circuit with extended dynamic range includes a first and second operational amplifier. The circuit's input voltage terminal is connected to the negative input of both operational amplifiers. The output of each operational amplifier directly drives the gates of two transistors which operate as a current mirror circuit. The two transistors associated with the first operational amplifier are p-channel transistors with their sources connected to VDD, and the two transistors driven by the second operational amplifier are n-channel transistors with their sources connected to ground. The drains of the first p-channel transistor and the first n-channel transistor are coupled back to the positive inputs of the first and second operational amplifiers respectively and also, through respective resistors, to a reference voltage. The drains of the second p-channel transistor and the second n-channel transistor are connected together to form a current output terminal.

Abstract: A waveform generating circuit, wherein a master clock signal is fed into a tapped string of adjustable delay lines, and the tapped delay outputs are used to control selection of scaled voltage fractions for output. The use of adjustable delay lines means that very high time-domain resolution can be achieved, simply by making a small adjustment to the value of a trimmable capacitor.

Abstract: An arbitration circuit (10) is provided for selecting between a serial port (19) and a parallel port (21) for interface with a system port (17) having a system data bus (14) and a system address bus (16). A RAM (12) is supported by the buses (14) and (16). The arbiter (10) is operable to store a count value in an arbitration byte (38) which is addressable by the parallel port (21). The serial port (19) is operable to transfer data through a serial/parallel converter (30) to the system data bus (14) and system address bus (16) during a serial port access window. The parallel port (21) is allowed to access the system data bus and address bus at all other times. A count value indicating the duration of time before occurrence of the access window is stored in the arbitration byte (38) and is accessible by the parallel port and a parallel CPU (24) to determine when address and data information can be transmitted to the arbiter (10) for transfer to RAM (12).

Abstract: An integrated circuit which includes a series resistor in the well tie. This resistor permits the wall to be used for clamping, without large current consumption due to the parastic bipolar device in the well.

Abstract: A low-power integrated circuit clock/calendar, wherein separate data busses are used for the time data and the alarm data. Conditional logic is used to only compare seconds bits (unless a match occurs, in which case higher-order bits are then compared). Thus, charging and discharging of the data busses (which carry the time data) occurs only when a data transition is occurring. A special clocked latch circuit is used to hold the potential of each line of the time data bus constant, except when the data on the bus is actually changing. These innovations help to provide extremely long battery lifetime, since charge is not consumed by unnecessarily charging and discharging busses. Preferably this bus architecture is combined with a low-power logic architecture.