Abstract: An integrated circuit which provides a low-power RS232 interface (or other serial interface). The integrated circuit receives separate power supply inputs for its own logic and for driving the serial line. Even if one of the power supply inputs fails, protection circuitry clamps floating nodes in the logic elements, and thereby avoids excessive current drain which might otherwise occur.

Abstract: An integrated circuit memory which includes at least some RAM/ROM hybrid columns. The RAM/ROM hybrid cells operate as normal SRAM cells forever, unless and until they are programmed to operate as ROM cells. Thus users who need the extra security permitted by ROM encoding can have this capability, while users who do not need ROM encoding can use off-the-shelf parts as RAM only.

Abstract: A peak detector circuit utilizes a comparator to compare an input signal to a peak voltage output signal. The output of the comparator enables a charging current source to charge a holding capacitor at a first rate when the input signal is greater than the peak voltage output signal and enables a discharging current source to discharge the holding capacitor at a second rate when the input signal is less than the peak voltage output signal. The capacitor voltage is coupled through the gate to source of an n-channel transistor and this source voltage forms the peak voltage output signal.

Abstract: In a battery-powdered system, a first integrated circuit provides a secondary power supply to a second integrated circuit, and also provides data signals in a serial protocol. The first integrated circuit steps down the secondary power supply when the reset-bar signal is being driven high. The second chip goes active whenever its reset-bar input exceeds its battery-voltage input.

Abstract: Apparatus for connecting a data storage module to an external circuit. A power supply terminal is connected between the module and the external circiut before signal terminals are connected. Apparatus includes a printed circuit board male card edge connector having selected card edge pins that extend farther than other card edge pins.

Abstract: A data communication system, including at least one base station and at least one portable module 120, wherein the portable module 120 transmits data on a high frequency, and the base station transmits data on a much lower frequency. Transmissions by the base station use a pulse-width modulation scheme where the most commonly used signals correspond to the shortest pulse. A "read" command is encoded as the same pulse width as one of the two write commands. Since the direction of data transmission is known in overhead, there will be no ambiguity.

Abstract: A physical interface configuration which provides rapid contact to a two-terminal coin-shaped electronic token data module. A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector interface circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token.

Abstract: A very compact and economical electronic data module, which includes battery-backed memory. The module is preferably coin-shaped, and the two faces of the module are isolated from each other. The module contains logic to perform serial transfer of the whole memory content on command, using a one-wire bus.

Abstract: A battery-backed integrated circuit, which receives battery power to maintain data (or logic states) when the system (external) power supply goes down. The battery power input is connected through a diode, so that the battery cannot be charged when the system power supply is active. The battery isolation diode is a junction diode, which is surrounded by a second junction. The second junction collects minority carriers which will be generated when the battery protection diode is forward biased (i.e. when the integrated circuit is being powered from the battery). Otherwise, minority carriers can diffuse to other junctions, to cause leakage currents which can significantly degrade the lifetime of a low-powered device.

Abstract: A latch circuit which is resistant to electrostatic discharge includes four cross-coupled NOR gate pairs located in the four corners of an integrated circuit chip, and a fifth cross-coupled NOR gate pair positioned generally in the center of the integrated circuit chip. The Q outputs, the Q outputs, the reset inputs, and the set inputs of each of the five cross-coupled NOR gate pairs are connected together such that a single cross-coupled NOR gate pair receiving an electrostatic discharge will be held in its present state by the action of the other four cross coupled NOR gate pairs which will either supply current or sink current in order to maintain the state of the Q and Q-bar outputs.

Abstract: A multi-layer integrated circuit package uses split or bifurcated leads on separate levels, connected in parallel, for conducting the power supply voltages to an integrated circuit chip inside the package. The bifurcated leads are joined at the external pins of the package, and are split adjacent the die bond site of the package. The split ends provide separate power supply voltage conductors to the output driver circuitry on the integrated circuit chip and to the other circuitry in the integrated circuit chip. The effects of the transient currents induced in the power supply leads of the package are substantially isolated from the power supply voltages applied to the other circuitry of the integrated circuit chip.

Abstract: A nonvolatile memory subsystem includes DRAMs and a battery-backed controller chip. The controller chip monitors the system power supply level to ascertain power fault conditions. When a power fault is detected, the controller provides the DRAMs with both a regulated supply voltage and appropriately timed refresh signals.After the system power supply has returned to specification, the controller continues to generate refresh control signals until the commands it to stop.

Abstract: A low-power low-voltage CMOS six-transistor static random access memory (SRAM), which can operate on a power supply voltage which is less than the sum of the NMOS and PMOS threshold voltages, does not include any analog or metastable sense amplifier stages. The selected cell is allowed to pull one of its bitline pair all the way down to ground. Thus, full logic levels appear on the bitline pair. Only one line of the bitline pair is connected to the following gate stage. Preferably bitline precharge transistors are connected to always pull up any unselected bitline pair.

Abstract: An integrated circuit filter wherein two digital inverters are used, with cutoff frequencies which bracket the desired passband frequency. (The cutoff frequency of the two digital inverters is selected by changing their RC time constants.) The inverter with the lower cutoff frequency has its output connected to the reset input of a counter, and the inverter with the higher cutoff frequency has its output connected to the clock input of a counter.

Abstract: A telecommunications FIFO provides an interface between two serial data transmission channels which have independent clocks and which can operate according to different protocols. The FIFO contains two storage registers each equal to a frame of data in length. Data is written into and read from alternate storage registers with the transfer between one register and the other occurring upon the receipt of write and read frame sync pulses respectively. At the receipt of each write frame sync pulse and read frame sync pulse, the read address location and the write address location respectively are sampled to determine if a FIFO overfill or empty condition is eminent. If such condition exists, the telecommunications FIFO does not switch registers, but rather rewrites the same register or rereads the same register respectively, to thereby perform a slip operation.

Abstract: A dynamic PLA timing circuit in a PLA ROM includes a first PLA line and the address section only of another PLA line. The address section of the first PLA line is connected to the true address lines and the address section of the other PLA line is connected to the complementary address lines. Shorting bars connecting the two PLA lines are formed around each pair of true and complementary address lines such that a conductive path is formed through the address sections for any address into the ROM. The data section is connected to the gates of every data transistor. However, the drains of all but one of the data transistors are not connected to their associated data line. The data line that is connected to the associated data transistor forms the output terminal of the timing circuit.

Abstract: A RF receiver with extremely low standby power consumption. To minimize power consumption during standby, the analog input from the antenna circuit (including tank resonator) is connected directly to the inputs of a comparator.Preferably two comparators are used, each connected to a separate antenna. Thus, a signal loss due to antenna nulls will be minimized.Preferably a following stage decodes a pulse-width-modulated (or burst-length-modulated) signal. If the length of pulses substantially exceeds the expected maximum, the following stage provides a control signal to reduce the gain of the input comparators.

Abstract: A test system in a standalone chassis without a power cord. The testing subsystem (e.g. a spectrophotometer) is microprocessor-controlled, and the microprocessor is disconnected from the battery during normal operation. An ancillary integrated circuit controls the power supply to the microprocessor, and periodically powers up a proximity sensor subsystem (e.g. a photodiode/LED pair), without powering up the microprocessor. The ancillary circuit powers up the microprocessor IF the proximity sensor subsystem, after being activated, indicates that a sample has been inserted by a user. The microprocessor can then operate the testing subsystem, and provide output data to a display driver accordingly.

Abstract: A physical interface configuration which provides rapid contact to a two-terminal coin-shaped electronic token data module. A slot, dimensioned to receive electronic tokens, includes a grounded contact positioned to make contact to the edge of a token which may be inserted, and two data contacts which are positioned to make contact to the opposite faces of the token. Each of the data contacts is connected to an open-collector interface circuit, including a pull-up resistor which will bring the potential of the contact high when the slot is empty. The token is shaped so that its edge, and one of its faces, are connected to the token's ground line, and the other face is the token's data line. Thus, when a token is inserted (no matter which way the token is facing), one of the two data contacts will be immediately pulled to ground, by short-circuiting across the ground plane of the token.

Abstract: A central processing unit with partitionable program and data memory includes a CRT (10) which is interfaced with an embedded program/data memory (14). The embedded memory (14) is a random access memory which has a user-defined partition address that defines an address above which all addresses are associated with program memory and below which all addresses are associated with data memory. The partition address is stored in a memory control register (106) and can be loaded therein upon initialization of the CPU (10). When the program address or the data address exceeds the address in the embedded memory (14), the CPU (10) is allowed to access external program memory (24) and external data memory (26). This is controlled by an allocation/range control logic circuit (108).