Patents Assigned to Adesto Technologies Corporation
  • Patent number: 10497868
    Abstract: A memory element can include a first electrode; at least one switching layer formed over the first electrode; a second electrode layer; and at least one conductive cap layer formed over the second electrode layer having substantially no grain boundaries extending through to the second electrode layer; wherein the at least one switching layer is programmable between different impedance states by application of electric fields via that first and second electrode. Methods of forming such memory elements are also disclosed.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 3, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: John Ross Jameson, III, Jeffrey Allan Shields, Kuei-Chang Tsai
  • Patent number: 10446747
    Abstract: A method can include, by operation of a controller circuit, writing data into a volatile memory portion formed in an integrated circuit substrate of a memory device. In response to first conditions, date can be written from the volatile memory portion into a nonvolatile memory portion formed in the same integrated circuit substrate as the volatile memory portion. The nonvolatile memory portion can store the data in two terminal memory elements re-programmable between at least two different resistance states.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Adesto Technology Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer
  • Patent number: 10409505
    Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: September 10, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Derric Lewis, John Dinh, Gideon Intrater, Nathan Gonzales
  • Patent number: 10396001
    Abstract: A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: August 27, 2019
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10290334
    Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 14, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Ishai Naveh
  • Patent number: 10275372
    Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: April 30, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Paul Hill
  • Patent number: 10191666
    Abstract: A method of controlling write parameter selection in a memory device, can include: (i) storing a configuration set number in a configuration register, where the configuration register is accessible by a user via an interface; (ii) receiving a write command from a host via the interface; (iii) comparing the stored configuration set number against set numbers in a register block to determine a match or a mismatch; (iv) downloading configuration bits from a memory array into the register block in response to the mismatch determination; (v) selecting a configuration set corresponding to the stored configuration set number from the register block in response to the match determination; and (vi) using the selected configuration set to perform a write operation on the memory device to execute the write command.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: January 29, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Derric Jawaher Herman Lewis, John Dinh, Nathan Gonzales
  • Patent number: 10181496
    Abstract: A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 15, 2019
    Assignee: Adesto Technologies Corporation
    Inventors: Ming Sang Kwan, Venkatesh P. Gopinath
  • Patent number: 10140062
    Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 27, 2018
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10042587
    Abstract: A memory device can include: a memory array comprising a plurality of memory cells; an interface configured to receive a suspend command and first and second write commands from a host, where the second write command is of higher priority and follows the first write command; a status register configured to store an automatic resume enable bit; a memory controller configured to suspend, in response to the suspend command, a first write operation that is executing the first write command on the memory array; the memory controller being configured to execute a second write operation on the memory array in response to the second write command; and the memory controller being configured to resume the first write operation upon completion of the second write operation in response to the automatic resume enable bit being set.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 7, 2018
    Assignee: Adesto Technologies Corporation
    Inventor: Bard M. Pedersen
  • Patent number: 10031869
    Abstract: In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: July 24, 2018
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Paul Hill
  • Publication number: 20180166130
    Abstract: A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.
    Type: Application
    Filed: May 2, 2016
    Publication date: June 14, 2018
    Applicant: Adesto technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Patent number: 9922684
    Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 20, 2018
    Assignee: Adesto Technologies Corporation
    Inventors: Bard M. Pedersen, Derric Lewis, John Dinh, Gideon Intrater, Nathan Gonzales
  • Patent number: 9852090
    Abstract: In one embodiment, a method of performing an active polling operation can include: (i) detecting a self-timed operation that is to be executed on a serial memory device; (ii) determining if an active polling mode has been enabled; (iii) determining when the self-timed operation has completed execution on the serial memory device; and (iv) providing a completion indication external to the serial memory device when the self-timed operation has completed execution and the active polling mode is enabled.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: December 26, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Paul Hill, Stephen T. Trinh, Dian Wang
  • Patent number: 9818939
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 14, 2017
    Assignee: ADESTO TECHNOLOGIES CORPORATION
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Yi Ma, Venkatesh P. Gopinath, Foroozan Sarah Koushan
  • Patent number: 9812200
    Abstract: A method of controlling an NVM device can include: (i) receiving, by an interface, a write command from a host; (ii) beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of NVM cells arranged in a plurality of array planes; (iii) receiving, by the interface, a read command from the host; (iv) suspending the write operation in response to detection of the read command during execution of the write operation; (v) beginning execution of a read operation on a second array plane in response to the read command; and (vi) resuming the write operation after the read operation has at least partially been executed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: November 7, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Shane Hollmer, Derric Lewis, Stephen Trinh
  • Patent number: 9812183
    Abstract: A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 7, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Gideon Intrater, Bard Pedersen, Ishai Naveh
  • Patent number: 9755142
    Abstract: A method can include forming a plurality of access transistors, including forming second semiconductor regions over an integrated circuit substrate that are doped to a second conductivity type, the second semiconductor regions being over and in contact with first semiconductor regions doped to a first conductivity type, and forming third semiconductor regions doped to the first conductivity type in contact with the second semiconductor regions; forming a plurality of conductive structures, over and in contact with the third semiconductor regions; and forming programmable impedance memory cells over and in contact with the conductive structures.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: September 5, 2017
    Assignee: Adesto Technologies Corporation
    Inventor: Ishai Naveh
  • Patent number: 9734902
    Abstract: In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 15, 2017
    Assignees: Adesto Technologies Corporation, Axon Technologies Corporation
    Inventors: Deepak Kamalanathan, Foroozan Sarah Koushan, Juan Pablo Saenz Echeverry, John Dinh, Shane C. Hollmer, Michael Kozicki
  • Patent number: 9729138
    Abstract: A circuit can include a signal section that includes a first signal transistor configured to operate in a subthreshold region to maintain the signal node at about VCC as VCC rises from a low level; a high threshold section that enables a current path from the signal node to the low power supply node only after a voltage at the detect node exceeds a level greater than a threshold voltage (Vt); and an output section having transistors with relatively long channels, for reduced crowbar current.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 8, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Nathan Gonzales, John Dinh