Abstract: A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.

Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Abstract: A method can include forming a bottom structure with a top surface and a side surface that form at least one edge; forming an opening with sloped sides through at least one insulating layer to expose at least a portion of the top surface of the bottom structure; forming a programmable layer over the at least one edge, in contact with the sloped sides of the opening and the top surface of the bottom structure; and forming a top layer over the programmable layer and opening; wherein the programmable layer is programmable between at least two different impedance states.

Abstract: A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.

Abstract: A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.

Abstract: In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) a word line pair configured to control access to the programmable impedance element, where the word line pair comprises first and second word lines; (iii) a PMOS transistor having a source coupled to the cathode, a drain coupled to a bit line, and a gate coupled to the first word line; and (iv) an NMOS transistor having a source coupled to the bit line, a drain coupled to the cathode, and a gate coupled to the second word line.

Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Abstract: In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells arranged in a plurality of array blocks, where each resistive memory cell is configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction, and to be erased to a high resistance state by application of an erase voltage in a reverse bias direction; (ii) a plurality of anode plates corresponding to the plurality of array blocks, where each resistive memory cell can include a resistive storage element having an anode coupled to one of the anode plates; (iii) an inactive ring surrounding the plurality of anode plates, where the inactive ring can include a same material as each of the plurality of anode plates; and (iv) a plurality of boundary cells located under the inactive ring.

Abstract: In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Abstract: A storage element can include a bottom structure having at least one edge formed by a top surface and a side surface; a programmable layer, programmable between at least two different impedance states, and formed over the at least one edge and in contact with a portion of the bottom structure; an insulating layer that extends above the top surface of the bottom structure having an opening to the bottom structure formed therein, the opening having sloped sides; and at least one top layer formed within the opening and in contact with the programmable layer. Methods of making such a storage element are also disclosed.

Abstract: Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.

Abstract: A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.

Abstract: A method can include programming programmable resistive elements (PREs) in a first integrated circuit (IC) device to establish functions of configurable circuits of the first IC device; and creating at least one second IC device by forming non-programmable connections based on resistive states of the PREs of the first IC device to provide the functions of the first IC device in the second IC device.

Abstract: In accordance with an embodiment of the present invention, a memory cell includes a two terminal access device disposed above a semiconductor substrate. The access device includes a two terminal resistive switching device having substantially zero retention. The two terminal resistive switching device has a low resistance state and a high resistance state. A memory device is disposed above the semiconductor substrate. The memory device is coupled to the access device.

Abstract: In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.

Abstract: A memory device can include a plurality of two terminal conductive bridging random access memory (CBRAM) type memory elements; at least one program transistor configured to enable a program current to flow through at least one memory element in response to the application of a program signal at its control terminal and a program bias voltage to the memory element; and an erase load circuit that includes at least one two-terminal diode-like load element, the erase load circuit configured to enable an erase current to flow through the load element and at least one memory element in a direction opposite to that of the program current.

Abstract: Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.

Abstract: A memory device can include at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.