Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: An integrated circuit may include multiple programmable metallization cells (PMCs) and a multiple bit lines. Each bit line may be connected to a anodes of a different set of PMCs, and provide a read data path from a selected one of the set of PMCs. Access devices may each provide a controllable impedance path between at least one cathode and a common source node.

Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.

Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.

Abstract: According to one embodiment of the present invention, a method of manufacturing an integrated circuit including a memory device includes, generating a solid electrolyte layer including a first solid electrolyte layer area and a second solid electrolyte layer area, the height of the top surface of the solid electrolyte layer within the second solid electrolyte layer area being lower than the height of the top surface of the solid electrolyte layer within the first solid electrolyte layer area; generating a conductive layer above the top surfaces of the first solid electrolyte layer area and the second solid electrolyte layer area; planarizing the top surface of the conductive layer such that the solid electrolyte layer is exposed within the first solid electrolyte layer area, however is covered by the conductive layer within the second solid electrolyte layer area; patterning the exposed solid electrolyte layer within the first solid electrolyte layer area.

Abstract: A method for producing a solid electrolyte material region for a memory element of a solid electrolyte memory cell. A first material is formed in substantially pure form. A thermal treatment is carried out in the presence of at least one second material, and the chalcogenide material of the solid electrolyte material region thereby being produced.