Abstract: A memory element programmable between different impedance states can include a first electrode layer comprising a semimetal or semiconductor (semimetal/semiconductor); a second electrode; and a switch layer formed between the first and second electrodes and comprising an insulating material; wherein atoms of the semimetal/semiconductor provide a reversible change in conductivity of the insulating material by application of electric fields.

Abstract: A memory device can include at least one array comprising a plurality of elements programmable between at least two different states, each state having a different time to a change in property under applied sense conditions; a read circuit configured to apply the sense conditions to selected elements and detect changes in property of the selected elements to generate read data; a latch circuit configured to store read data from the read circuit; and a transfer path configured to provide a parallel data transfer path between the read circuit and the latch circuit.

Abstract: A memory device can include a plurality of memory elements, each including first electrode having a surrounding first electrode side surface in a lateral direction; a memory material surrounding the first electrode side surface in the lateral direction, the memory material being programmable between at least two different impedance states in response to electric fields; and a second electrode formed around the memory material in the lateral direction.

Abstract: In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.

Abstract: Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.

Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.

Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

Abstract: A memory element can include an opening formed within at least one insulating layer formed on an etch stop layer that exposes a first electrode portion and the etch stop layer at a bottom of the opening; a second electrode portion, formed on at least a side surface of the opening and in contact with the first electrode portion, the second electrode portion not filling the opening and being substantially not formed over a top surface of the at least one insulating layer; and at least one memory layer formed on a top surface of the at least one insulating layer and in contact with the second electrode portion, the at least one memory layer being reversibly programmable between at least two impedance states. Methods of forming such memory elements are also disclosed.

Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

Abstract: Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.

Abstract: A memory device can include a load circuit coupled in series with at least one memory element between two nodes and configured to enable a programming current to flow through the memory element to lower its impedance, and configured to enable an erase current to flow through the element in a direction opposite to the program current, the erase current varying in response to an erase voltage applied across the two nodes as the memory element impedance increases.

Abstract: An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.

Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.

Abstract: A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.

Abstract: An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.

Abstract: A memory device can include at least two ports for transferring data to and from the memory device; and plurality of memory cells, each memory cell including at least one element programmable between different impedance states, and a plurality of access devices, each access device providing a current path between the element and a different one of the ports.

Abstract: A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

Abstract: A memory device can include a plurality of memory elements programmable between different impedance states; and circuits configured to apply first electrical conditions to one group of memory elements and second electrical conditions, different from the first electrical conditions, to another group of memory elements to vary a speed of an access operation to the different groups of memory elements.

Abstract: Structures and methods of operating a programmable impedance element are disclosed herein. In one embodiment, a method of operating a programmable impedance element can include: (i) determining an operation to be performed on the programmable impedance element, where the programmable impedance element includes a solid electrolyte between an active electrode and an inert electrode; (ii) in response to the determined operation being a program operation, programming the programmable impedance element by completing formation of a conductive path from a partial conductive path between the active and inert electrodes; and (iii) in response to the determined operation being an erase operation, erasing the programmable impedance element by substantially dissolving the conductive path, and then by forming the partial conductive path.

Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.