Abstract: A slope rate compensation circuit includes a source follower level-shift amplifier, a capacitor, a first resistor and a second resistor. The source follower level-shift amplifier includes a first transistor and a second transistor. The first transistor allows a first current to flow therein, the second transistor allows a second current to flow therein, and the first current increases with the second current. The capacitor is connected to the source terminal of the first transistor. The first resistor is connected to the source terminal of the second transistor. The second resistor allows a third current to flow therein, and the third current increases with the second current. The second resistor is related to the output voltage of the slope rate compensation circuit.

Abstract: A frequency divider circuit comprises a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate.

Abstract: A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage.

Abstract: An LED apparatus comprises a PCB and a plurality of LEDs packaged on the PCB. The PCB materials on the area between the plurality of LEDs are partially removed to form a plurality of gaps, wherein the gaps are immediately close to the LEDs and directly dissipate heat of the LEDs.

Abstract: A PWM comprises a voltage transformation module, a voltage-sensing module and a timer. The voltage transformation module is configured to transform an input voltage into an output voltage. The voltage-sensing module is coupled to the voltage transformation module and configured to detect a voltage of a first terminal, wherein the voltage of the first terminal is proportional to the output voltage. The timer is configured to measure the time duration for which the voltage of the first terminal is lower than a reference voltage, wherein the timer initiates a short circuit signal when the time duration is greater than a predetermined value.

Abstract: An over current protection circuit for low dropout regulator comprises a sense transistor, a sense resistor, an operational amplifier and a first transistor. The sense transistor senses the current flowing through the power transistor. The sense resistor is coupled to the sense transistor and shares the same current flowing through the sense transistor. The operational amplifier outputs a control signal according to the voltage across the sense resistor and a reference voltage. The first transistor controls the power transistor according to the control signal.

Abstract: A low dropout regulator comprises a depletion mode NMOS transistor, a switch and an error amplifier. The source electrode of the depletion type NMOS transistor is coupled to a feedback circuit. The switch, controlled by a control signal, connects a supply voltage to the drain electrode of the depletion mode NMOS transistor. The non-inverting input terminal of the error amplifier is coupled to a reference voltage. The output terminal of the error amplifier is coupled to the gate electrode of the depletion mode NMOS transistor. The inverting input terminal of the error amplifier is coupled to the feedback circuit.

Abstract: An LED driver circuit comprises a buck-boost converter circuit and a resistor. The cathode terminal of the LED is connected to the output terminal of the buck-boost converter circuit. The anode terminal of the LED is connected to a reference voltage. The resistor connects the anode terminal of the LED to a power input.

Abstract: A frequency divider circuit comprises a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate.

Abstract: An LDO with over-current protection includes a first and a second P-type transistor, a sensing resistor, a comparator, and an error amplifier. The channel aspect ratio of the first P-type transistor is much higher than that of the second P-type transistor. The first P-type transistor generates output voltage source according to input voltage source and current control signal. The sensing resistor is coupled among the input voltage source, the second P-type transistor, and the comparator, providing a sensing voltage. The comparator generates a current limiting signal according to first reference voltage and the sensing voltage. When the current limiting signal enables the error amplifier, the error amplifier adjusts voltage of the current control signal according to second reference voltage and voltage divided from the output voltage source; when the current limiting signal disables the error amplifier, voltage of the current control signal is not adjusted.

Abstract: A power switch circuit exhibiting over current and short circuit protections comprises a power-driving unit, a sense unit and a feedback controller circuit. The power-driving unit provides power to a load circuit from a power supply. The sense unit senses the output current of the power-driving unit. The feedback controller circuit controls the power-driving unit and the sense unit. When the output current of the power-driving unit exceeds a threshold, the output current is limited to an over current protection current level. When the resistance of the load circuit is approximately zero, the output current of the power-driving unit is limited to a short circuit protection current level.

Abstract: A feedback signal sensing method includes the steps of: providing a pulse width modulation (PWM) signal having a period; charging a capacitor by a current source during a pulse duration of the period, so as to form an equivalent slope compensation ramp signal; conducting an inductor current flowing from a boost inductor to flow through an equivalent resistor during the pulse duration of the period, so as to form an equivalent inductor current signal; and using a coupling characteristic of the capacitor together with the equivalent slope compensation ramp signal and the equivalent inductor current signal to form a feedback signal.

Abstract: An LDO with fast current limit includes P-type transistor, an error amplifier, an adjustable reference voltage circuit for generating an adjustable reference voltage, and an N-type transistor. The P-type transistor includes a first end coupled to the input voltage source, a second end for outputting an output voltage source, and a control end for receiving a current control signal in order to control the current of the output voltage source. The error amplifier generates the current control signal according to the reference voltage and a voltage divided from the output voltage source. N-type transistor includes a first end coupled to the output end of the error amplifier, a second end coupled to the input voltage source, and a control end for receiving the adjustable reference voltage. When the N-type transistor is turned on, the voltage of the current control signal is clamped by the adjustable reference voltage.

Abstract: A multi-input operational amplifier comprises two transconductors, two current mirrors, and a current source. Each transconductor generates a current according to a corresponding voltage difference. When the voltage difference is less than or equal to zero, the current is a constant. When the voltage difference exceeds zero, the current is proportional to the voltage difference.

Abstract: A slope rate compensation circuit includes a source follower level-shift amplifier, a capacitor, a first resistor and a second resistor. The source follower level-shift amplifier includes a first transistor and a second transistor. The first transistor allows a first current to flow therein, the second transistor allows a second current to flow therein, and the first current increases with the second current. The capacitor is connected to the source terminal of the first transistor. The first resistor is connected to the source terminal of the second transistor. The second resistor allows a third current to flow therein, and the third current increases with the second current. The second resistor is related to the output voltage of the slope rate compensation circuit.

Abstract: A pulse width modulation controller comprises a disabling unit, a level sensor and an over current protector. These three devices are all coupled to a multi-function node for accomplishing a disable function, input level sensing, and over-current protection, respectively.

Abstract: A PWM controller for controlling a switching voltage regulator comprises a first comparator, a second comparator and a third comparator. The first comparator is configured to detect voltages of a first node and a second node so as to determine whether to stop the PWM controller. The PWM controller is stopped if a first potential is lower than a threshold, and the first potential derives from the voltage of the first node by a level shift of a first voltage difference. The second comparator is configured to detect the voltage of the first node and then to compare the voltage with a power reference voltage so as to determine whether the PWM controller receives necessary power. The third comparator is configured to compare the voltage of the second node with an enable reference voltage so as to determine whether to disable the PWN controller.

Abstract: A control circuit comprises a PWM control circuit and a PWM skip control circuit. The PWM control circuit controls a switching circuit. The switching circuit acts as a current source for an output circuit and a load circuit. The PWM skip control circuit controls the operation of the PWM control circuit. When the output current of the switching circuit is below a predetermined threshold, the PWM skip control circuit stops the operation of the PWM control circuit. When the output voltage of the switching circuit is below a predetermined threshold, the PWM skip control circuit resumes the operation of the PWM control circuit.

Abstract: A clamp circuit comprises a first transistor, a second transistor and a voltage-dividing circuit. The first transistor has a source terminal connected to a reference voltage, and has a drain terminal grounded through a current source. The second transistor has a gate terminal connected to the gate and drain terminals of the first transistor, and has a drain terminal grounded. The voltage-dividing circuit is connected to an input voltage end, an output voltage end and a source terminal of the second transistor for providing a clamping voltage.

Abstract: A PWM controller applied to a switching voltage regulator comprises a disabling circuit, a power-sensing circuit, an over-current protection circuit and a PWM logic circuit. The disabling circuit is connected to an external frequency compensation circuit for detecting a voltage used to stop the operation of the PWM controller. The power-sensing circuit is configured to stop the operation of the PWM controller if the input voltage of the high side switch is lower than a threshold. The over-current protection circuit is configured to monitor current flowing through the output circuit, and the over-current protection circuit generates an over-current protection signal when the current exceeds a threshold. The PWM logic circuit is connected to the outputs of the disabling circuit, power-sensing circuit and over-current protection circuit.