Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: A trim fuse circuit includes a metal fuse, a trim pad coupled to the first end of the metal fuse, a first transistor coupled to the first end of the metal fuse, a second transistor coupled to the second end of the metal fuse, an inverter coupled to the second end of the metal fuse, a switch coupled to the second end of the metal fuse, and a common trim pad coupled to the control end of the switch. The inverter outputs a data signal according to the status of the metal fuse. The trim pad can be disposed on the scribe line of a wafer. When the trim pad is cut and accordingly connects to the substrate of the wafer, the data signal is not affected.

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Abstract: A slope rate compensation circuit includes a source follower level-shift amplifier, a capacitor, a first resistor and a second resistor. The source follower level-shift amplifier includes a first transistor and a second transistor. The first transistor allows a first current to flow therein, the second transistor allows a second current to flow therein, and the first current increases with the second current. The capacitor is connected to the source terminal of the first transistor. The first resistor is connected to the source terminal of the second transistor. The second resistor allows a third current to flow therein, and the third current increases with the second current. The second resistor is related to the output voltage of the slope rate compensation circuit.

Abstract: A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.

Abstract: Exemplary systems and methods for charging a battery with a digital charge reduction loop are described herein. In some embodiments, a system comprises an exemplary digital charge reduction loop which comprises a circuit for determining a charge-current adjustment signal, a counter for generating a digital count value, and a digital-to-analog converter. The circuit for determining a charge-current adjustment signal may base the determination on a source voltage of an input source. The counter may generate a digital count value based on the charge-current adjustment signal. The digital-to-analog converter (DAC) may generate a DAC control signal based on the digital count value of the counter, the DAC control signal being representative of an amount of charge current to be used to charge a battery.

Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Abstract: All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.

Abstract: A frequency divider circuit comprises a plurality of T flip-flops, a first transmission gate, a second transmission gate and an inverter. The plurality of T flip-flops is connected in series. The output of the inverter is connected to a clock input of a first T flip-flop. The first transmission gate connects a clock signal and the other clock input of the first T flip-flop and the input of the inverter. The second transmission gate connects the inverted signal of the clock signal and the output of the first transmission gate.

Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

Abstract: Devices, such as mobile devices, may be exposed to short circuit and output overload events. To protect against such events, mobile devices typically include circuitry to limit currents so as not to exceed a pre-programmed current limit. Various embodiments of the present invention include devices and methods for detecting pre-programmed current limits and for limiting currents in response to such detection. In some embodiments, both the current limit detector and the current limit controller circuitry include scaled current switches. The scaling may be substantially similar between the programmed-current limit detector and the current limit controller circuitry.

Abstract: A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: Various integrated circuit devices, in particular a transistor, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: A battery charger apparatus for charging a battery, comprises a charge-current control circuit for receiving a charge-current control signal to control an amount of charge current being drawn from an input source, e.g.

Abstract: An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

Abstract: An LDO with over-current protection includes a first and a second P-type transistor, a sensing resistor, a comparator, and an error amplifier. The channel aspect ratio of the first P-type transistor is much higher than that of the second P-type transistor. The first P-type transistor generates output voltage source according to input voltage source and current control signal. The sensing resistor is coupled among the input voltage source, the second P-type transistor, and the comparator, providing a sensing voltage. The comparator generates a current limiting signal according to first reference voltage and the sensing voltage. When the current limiting signal enables the error amplifier, the error amplifier adjusts voltage of the current control signal according to second reference voltage and voltage divided from the output voltage source; when the current limiting signal disables the error amplifier, voltage of the current control signal is not adjusted.

Abstract: A feedback signal sensing method includes the steps of: providing a pulse width modulation (PWM) signal having a period; charging a capacitor by a current source during a pulse duration of the period, so as to form an equivalent slope compensation ramp signal; conducting an inductor current flowing from a boost inductor to flow through an equivalent resistor during the pulse duration of the period, so as to form an equivalent inductor current signal; and using a coupling characteristic of the capacitor together with the equivalent slope compensation ramp signal and the equivalent inductor current signal to form a feedback signal.

Abstract: An LDO with fast current limit includes P-type transistor, an error amplifier, an adjustable reference voltage circuit for generating an adjustable reference voltage, and an N-type transistor. The P-type transistor includes a first end coupled to the input voltage source, a second end for outputting an output voltage source, and a control end for receiving a current control signal in order to control the current of the output voltage source. The error amplifier generates the current control signal according to the reference voltage and a voltage divided from the output voltage source. N-type transistor includes a first end coupled to the output end of the error amplifier, a second end coupled to the input voltage source, and a control end for receiving the adjustable reference voltage. When the N-type transistor is turned on, the voltage of the current control signal is clamped by the adjustable reference voltage.