Abstract: Plasma processing systems and methods are disclosed. The method includes generating and sustaining a plasma in a plasma chamber and producing a surface potential on a surface of a workpiece in the plasma chamber by applying, with a bias supply, an output waveform to a bias electrode within the plasma chamber where the output waveform has a repetition period, T. A waveform dataset is produced to represent the output waveform of the bias supply during the repetition period, T, and the waveform dataset is sent to one or more other pieces of equipment connected to the plasma chamber. A synchronization pulse with a synchronization-pulse-repetition-period is sent to the one or more other pieces of equipment connected to the plasma chamber to enable synchronization among the one or more other pieces of equipment.

Abstract: Disclosed are power supply systems and methods of operating the same. An exemplary power supply system includes a primary rectifier configured to rectify an AC voltage to produce a bus voltage on a DC bus and a voltage monitor configured to monitor the AC voltage. A capacitor is switchably coupled to the DC bus via a switch and a charger is configured to charge the capacitor with power from the DC bus. A switch controller is configured to close, in response to the voltage monitor indicating a sag in at least one phase of the AC voltage, the switch to enable the capacitor to discharge to the DC bus.

Abstract: Systems and methods for operating switches of a power supply are disclosed. The method includes generating power with a power source and switchably coupling the power source to an output of the power supply. One or more switches are opened and closed to generate a voltage waveform at the output, and in addition, the one or more switches are opened and closed to reduce a temperature differential that occurs between a low temperature and a high temperature of each switch by increasing the low temperature of each switch.

Abstract: A controller for a PIN diode coupled to a forward bias supply in series with an inductor by way of a first switch and coupled with a reverse bias supply in series with the inductor by way of a second switch. In reverse biasing the PIN diode, energy is recovered from the PIN diode, and possibly other components such as a reactance element (e.g., capacitor) coupled with the PIN diode, by momentarily disconnecting the reverse bias supply. In forward biasing the PIN diode, energy is recovered from the PIN diode, and possibly other components, by momentarily disconnecting the forward bias supply.

Abstract: Plasma processing systems and methods are disclosed. The plasma processing system includes a high-frequency generator configured to deliver power to a plasma chamber and a low-frequency generator configured to deliver power to the plasma chamber. A filter is coupled between the plasma chamber and the high-frequency generator, and the filter suppresses mixing products of high frequencies produced by the high-frequency generator and low frequencies produced by the low-frequency generator.

Abstract: Systems and methods for plasma processing are disclosed. An exemplary system may include a plasma processing chamber including a source to produce a plasma in the processing chamber and at least two bias electrodes arranged within the plasma processing chamber to control plasma sheaths proximate to the bias electrodes. A chuck is disposed to support a substrate, and a source generator is coupled to the plasma electrode. At least one bias supply is coupled to the at least two bias electrodes, and a controller is included to control the at least one bias supply to control the plasma sheaths proximate to the bias electrodes.

Abstract: An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

Abstract: This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

Abstract: A variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and coupled to the port. The variable capacitor bank further includes capacitor modules disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor branch electrically coupled to the module input, the switched capacitor branch including a capacitor and a switch element in series with the capacitor. In certain implementations, one or more of the capacitor modules may include at least one second switched capacitor branch. The capacitor modules may further include an unswitched, or “floor”, capacitor that provides a minimum or otherwise known capacitance of the capacitor module. Each capacitor module may further be grounded by being electrically coupled to the conductive housing.

Abstract: Systems and methods for plasma processing are disclosed. A method includes applying power to a plasma processing chamber during a first processing step and generating, during the first processing step, a first plasma sheath voltage between a substrate and a plasma. During a second processing step (that follows the first processing step), power is applied to the plasma processing chamber and a different plasma sheath voltage is applied between the substrate and the plasma.

Abstract: This disclosure is generally directed to controlling energy distribution to a load, especially when anomalous events are detected. Benefits of the present disclosure include minimizing the length of a discharge event, mitigating the effects of an electrical discharge, and to improvements in inducing the ignition of a plasma. Methods and systems consistent with the present disclosure improve the control of operating conditions within a chamber and improve the ability for more rapidly initiating plasma ignition in a chamber.

Abstract: A coating system that reduces parasitic currents that may cause crazing in coatings on a substrate. In one example, the system includes a pair of low impedance shunt paths to ground for parasitic AC currents generated from the plasma in the chamber. The low impedance shunts may be provided through a balanced triaxial connection between a power supply of each chamber and the magnetrons of each chamber. In another example, potential differences between adjacent chambers are minimized through synchronized power supply signals between chambers.

Abstract: A power supply system controls the source impedance of a generator in real time utilizing two amplifiers having asymmetrical power profiles in reference to a nominal load impedance that are diametrically opposite in reference to the nominal load impedance. Variations in power profiles may be achieved by using different topologies for each of the amplifiers or implementing a phase delay network. The output power from the first and second amplifiers may be combined using a combiner circuit or device and the output power from the combiner is transmitted to a plasma load. The output power of each amplifier may be independently controlled to alter one or more characteristics of the output power signal provided by the individual amplifiers. By changing the ratio of the output power of the first amplifier to the output power of the second amplified, the source impedance of the generators may be varied in real time.

Abstract: An apparatus utilizing additive interleaved switchmode (PWM) power conversion stages, having minimal or no output filter, to achieve high bandwidth or even ideally instantaneous power conversion. The additive process may involve voltage stacking of isolated PWM converters, which are interleaved in time, or may involve a single input power supply and inductively combining output currents of PWM power converters interleaved in time, with either additive circuit having minimal or no output filtering. This circuit may overcome limitations for the frequency of feedback control loops once thought to be physical limitations, such as, fundamental switching frequency, output filter delay and the Nyquist criteria.

Abstract: A controller for a PIN diode coupled to a forward bias supply in series with an inductor by way of a first switch and coupled with a reverse bias supply in series with the inductor by way of a second switch. In reverse biasing the PIN diode, energy is recovered from the PIN diode, and possibly other components such as a reactance element (e.g., capacitor) coupled with the PIN diode, by momentarily disconnecting the reverse bias supply. In forward biasing the PIN diode, energy is recovered from the PIN diode, and possibly other components, by momentarily disconnecting the forward bias supply.

Abstract: This disclosure relates to apparatus and methods for radio-frequency (RF) switching circuits, and more particularly for a PIN diode driver circuit for high speed, high repetition rate and/or high power applications. The PIN diode driver may include a dual voltage reverse bias provided to the PIN diode, which dual voltage reverse bias may be provided by a first, relatively lower voltage, power supply and a second, relatively higher voltage, power supply. The relatively lower voltage is to discharge an intrinsic layer of the PIN diode at a lower voltage than during reverse bias of the PIN diode at the second relatively higher bias voltage in order to reduce overall power consumption.

Abstract: A RF amplifier is provided that includes a plurality of switch modules connected in a cascade configuration and divided into disjoint sets in accordance with their corresponding distinct peak DC voltages or currents, each switch module including a plurality of switch devices connected in a half-bridge or full-bridge circuit and a DC voltage or current source electrically connected with the half-bridge or full-bridge circuit, and a control circuit configured to determine an output voltage or current of the RF amplifier at the next switching interval, examine the states of the switching devices in the respective switch modules to identify a combination of least-recently-switched switching devices within each set of switch modules that, when switched to an opposite state, will produce the determined output voltage or current, and switch to an opposite state, at the next switching interval, the switching devices in the identified combination.

Abstract: An impedance matching system includes an impedance matching network coupled between an alternating current (AC) generator and electrodes of a plasma chamber. The AC generator is configured to generate a multi-level pulse signal of cyclically recurring pulse intervals with differing amplitude levels. A controller or other device identifies each recurring pulse interval, and for each pulse interval, determines an impedance mis-match level between the AC generator and the electrodes, adjusts a configuration of the impedance matching network according to the determined impedance mis-match level, and stores information associated with the adjusted configuration.

Abstract: A gate drive circuit includes a lower limit clamping circuit, an upper limit clamping circuit, and an averaging circuit. The lower limit clamping circuit clamps the input node of a transistor at a minimum voltage with respect to the common node of the transistor, while the upper limit clamping circuit clamps the input node of the transistor at a maximum voltage with respect to the common node of the transistor and the averaging circuit sets the average voltage of the input node with respect to the common node over a specified period of time. The transistor including a common node, an output node and an input node receives the input signal. Controlling the upper limit, lower limit and average value in conjunction with fast transitions between the lower and upper limits controls the duty cycle of the input signal.

Abstract: A method for controlling a generator connected to a load involving obtaining a first measured value (M1) related to a forward power calculated with respect to reference impedance (Zc). The method involves adjusting an output of the generator in order that M1 tends to a first setpoint. The method further involves adjusting the first setpoint in order to adjust a second measured value (M2) of a conventional measure of generator output towards a second setpoint, where wherein the forward power calculated with respect to the reference impedance (Zc) is equal to: ? v + Z c ? i ? 2 2 ? real ? ? ( Z c ) where v is a voltage at a reference point, which may be between the generator and load input, and i is a current flowing relative to the load (e.g., current toward the load or a negative value of current toward the generator) at the reference point.