Patents Assigned to Advanced Micro Device, Inc.
  • Publication number: 20230205433
    Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230206540
    Abstract: A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to obtain a bounding box for a compressed box data item of the compressed box node.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Chen Huang
  • Publication number: 20230206539
    Abstract: Methods and systems are disclosed for traversing nodes in a BVH tree by an intersection engine. Techniques disclosed comprise receiving, by the intersection engine, a traversal instruction, including a tracing-mode, ray data, and an identifier of a node to be traversed. Where the tracing-mode includes a closest hit mode and a first hit mode. If the node to be traversed is an internal node, the intersection engine determines, based on the tracing-mode, an order in which children nodes of the node are to be next traversed and output identifiers of the children nodes in the determined order.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Alexandre Tsakok, Skyler Jonathon Saleh
  • Publication number: 20230205680
    Abstract: Methods and systems are disclosed for emulating, in a platform, the performance of a target platform. Techniques disclosed include receiving, by the platform, values of system features, associated with a target performance of the target platform; and setting, by the platform, one or more configuration knobs, based on the received values of system features, to match a performance of the platform to the target performance of the target platform.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Richard E. George, Vidyashankar Viswanathan, Michael Y. Chow
  • Publication number: 20230205584
    Abstract: A disclosed technique includes allocating a first set of resource slots for a first execution instance of a pipeline shader program; correlating the first set of resource slots with graphics pipeline passes; and on a second execution instance of the pipeline shader program, assigning resource slots, from the first set of resource slots, to the graphics pipeline passes, based on the correlating.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Zhuo Chen, Steven J. Tovey
  • Publication number: 20230205420
    Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
  • Publication number: 20230206542
    Abstract: A technique for performing ray tracing operations is provided. The technique includes processing small bounding box nodes in a box intersection test circuit to generate intersection test results for the small bounding box nodes; and processing large bounding box nodes in the box intersection test circuit to generate intersection test results for the large bounding box nodes.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Fataneh F. Ghodrat, Jeffrey Christopher Allan, Skyler Jonathon Saleh
  • Publication number: 20230205544
    Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to execute a forward activation of the neural network using a low precision floating point (FP) format, scale up values of numbers represented by the low precision FP format and process the scaled up values of the numbers as non-zero values for the numbers. The processor is configured to scale up the values of one or more numbers, via scaling parameters, to a scaled up value equal to or greater than a floor of a dynamic range of the low precision FP format. The scaling parameters are, for example, static parameters or alternatively, parameters determined during execution of the neural network.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Hai Xiao
  • Publication number: 20230206509
    Abstract: Methods and systems are disclosed for encoding a Morton code. Techniques disclosed comprise receiving location vectors associated with primitives, where the primitives are graphical elements spatially located within a three-dimensional scene. Techniques further comprise determining a code pattern comprising a prefix pattern and a base pattern, and, then, coding each of the location vectors according to the code pattern.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: John Alexandre Tsakok
  • Publication number: 20230206379
    Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Mangesh P. Nijasure, Rakan Z. Khraisha, Manu Rastogi
  • Publication number: 20230207038
    Abstract: Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.
    Type: Application
    Filed: December 29, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
  • Publication number: 20230205608
    Abstract: A disclosed technique includes executing, for a first wavefront, a barrier arrival notification instruction, for a first barrier, indicating arrival at a first barrier point; performing, for the first wavefront, work prior to the first barrier point; executing, for the first wavefront, a barrier check instruction; and executing, for the first wavefront, at a control flow path based on a result of the barrier check instruction.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Brian Emberling, Joseph L. Greathouse
  • Publication number: 20230206541
    Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing through a bounding volume hierarchy to an instance node; performing an instance node transform using common circuitry; traversing to a leaf node of the bounding volume hierarchy; and performing an intersection test for the leaf node using the common circuitry.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Fataneh F. Ghodrat, Jeffrey Christopher Allan
  • Publication number: 20230206113
    Abstract: A technique for processing images is disclosed. The technique includes tracking accesses, by a machine learning system, to individual features of a set of features, to generate an access count for each of the individual features; generating a rank for at least one of the individual features of the set of features based on the access count; and assigning the at least one of the individual features to a level of a memory hierarchy based on the rank.
    Type: Application
    Filed: December 28, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Sergey Blagodurov
  • Publication number: 20230205297
    Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
  • Patent number: 11687251
    Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 27, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
  • Patent number: 11687460
    Abstract: Methods, devices, and systems for GPU cache injection. A GPU compute node includes a network interface controller (NIC) which includes NIC receiver circuitry which can receive data for processing on the GPU, NIC transmitter circuitry which can send the data to a main memory of the GPU compute node and which can send coherence information to a coherence directory of the GPU compute node based on the data. The GPU compute node also includes a GPU which includes GPU receiver circuitry which can receive the coherence information; GPU processing circuitry which can determine, based on the coherence information, whether the data satisfies a heuristic; and GPU loading circuitry which can load the data into a cache of the GPU from the main memory if on the data satisfies the heuristic.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 27, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. LeBeane, Walter B. Benton, Vinay Agarwala
  • Patent number: 11687281
    Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 27, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Guanhao Shen, Ravindra Nath Bhargava
  • Patent number: 11687456
    Abstract: An electronic device that handles memory accesses includes a memory and a processor that supports a plurality of streams. The processor acquires a graph that includes paths of operations in a set of operations for processing instances of data through a model, each path of operations including a separate sequence of operations from the set of operations that is to be executed using a respective stream from among the plurality of streams. The processor then identifies concurrent paths in the graph, the concurrent paths being paths of operations between split points at which two or more paths of operations diverge and merge points at which the two or more paths of operations merge. The processor next executes operations in each of the concurrent paths using a respective stream, the executing including using memory coloring for handling memory accesses in the memory for the operations in each concurrent path.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: June 27, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mei Ye
  • Publication number: 20230198528
    Abstract: A apparatus includes a reference signal generator, a droop detection circuit, a digital frequency-locked loop (DFLL), and a DFLL control circuit. The reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value. The droop detection circuit converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal. The DFLL provides a clock signal for synchronizing circuitry within a domain of the monitored supply voltage. The DFLL control circuit, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Kaushik Mazumdar, Joyce Cheuk Wai Wong, Naeem Ibrahim Ally, Stephen Victor Kosonocky