Patents Assigned to ADVANCED MICRO DEVICES (AMD)
  • Method and apparatus for an HDR hardware processor inline to hardware encoder and decoder
    Patent number: 11503310
    Abstract: A device includes an encoder, decoder, codec or combination thereof and inline hardware conversion units that are operative to convert stored image data into one of: an HDR/WCG format and an SDR/SCG format during the conversion process. Each of the inline hardware conversion units is operative to perform the conversion process independent of another read operation with the memory that stores the image data to be converted. In one example, an encoding unit is operative to perform a write operation with a memory to store the converted image data after completing the conversion process. In another example, a decoding unit is operative to perform a read operation with the memory to retrieve the image data from the memory before initiating the conversion process. In another example, an encoder/decoder unit is operative to perform at least one of: the read operation and the write operation.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 15, 2022
    Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Lei Zhang, David Glen, Kim A. Meinerth
  • Method and apparatus for data transmission mitigating interwire crosstalk
    Patent number: 11496241
    Abstract: Data transmission mitigating interwire crosstalk including: dividing a data block to be transmitted from a transmitter to a receiver across a set of signal wires into sub-blocks; encoding each of the sub-blocks into a plurality of codewords; selecting, for each sub-block by a cost function, one of the codewords that is less likely to introduce interwire crosstalk; transmitting the selected codewords; and updating the cost function at the transmitter with feedback from the receiver.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Seyedmohammad Seyedzadehdelcheh
  • Page table walker with page table entry (PTE) physical address prediction
    Patent number: 11494300
    Abstract: Methods and apparatus provide virtual to physical address translations and a hardware page table walker with region based page table prefetch operation that produces virtual memory region tracking information that includes at least: data representing a virtual base address of a virtual memory region and a physical address of a first page table entry (PTE) corresponding to a virtual page within the virtual memory region. The hardware page table walker, in response to the TLB miss indication, prefetches a physical address of a second page table entry, that provides a final physical address for the missed TLB entry, using the virtual memory region tracking information. In some implementations, the prefetching of the physical PTE address is done in parallel with earlier levels of a page walk operations.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Gabriel H. Loh
  • Memory controller with a plurality of command sub-queues and corresponding arbiters
    Patent number: 11494316
    Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Brendan T. Mangan
  • Circuit board with compact passive component arrangement
    Patent number: 11495588
    Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 8, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Milind Bhagavat, Rahul Agarwal
  • Pipeline including separate hardware data paths for different instruction types
    Patent number: 11494192
    Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: November 8, 2022
    Assignees: Advanced Micro Devices, Inc., ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventors: Jiasheng Chen, YunXiao Zou, Bin He, Angel E. Socarras, QingCheng Wang, Wei Yuan, Michael Mantor
  • Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
    Patent number: 11487447
    Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 1, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Mahzabeen Islam, Shaizeen Aga, Nuwan Jayasena, Jagadish B. Kotra
  • Back side metallization
    Patent number: 11488922
    Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: November 1, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Thomas P. Dolbear, Daniel Cavasin, Sanjay Dandia
  • Semiconductor chip with redundant thru-silicon-vias
    Patent number: 11469212
    Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 11, 2022
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Bryan Black, Michael Z. Su, Gamal Refai-Ahmed, Joe Siegel, Seth Prejean
  • Multirow semiconductor chip connections
    Patent number: 11469183
    Abstract: A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 11, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat
  • Graded throttling for network-on-chip traffic
    Patent number: 11470004
    Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 11, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Narendra Kamat
  • System and method for controlling electrical current supply in a multi-processor core system via instruction per cycle reduction
    Patent number: 11460879
    Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: October 4, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man, Gokul Subramani Ramalingam Lakshmi Devi, Xiaojie He
  • System and method for providing system level sleep state power savings
    Patent number: 11449346
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
  • Controlling prediction functional blocks used by a branch predictor in a processor
    Patent number: 11442727
    Abstract: An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 13, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Varun Agrawal, John Kalamatianos
  • Optimizing runtime alias checks
    Patent number: 11435987
    Abstract: Optimizing runtime alias checks includes identifying, by a compiler, a base pointer and a plurality of different memory accesses based on the base pointer in a code loop; generating, by the compiler, a first portion of runtime code to determine a minimum access and a maximum access of the plurality of different memory accesses; and generating, by the compiler, a second portion of runtime code including one or more runtime alias checks for the minimum access and one or more runtime alias checks for the maximum access.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 6, 2022
    Assignee: ADVANCED MICRO DEVICES, INC
    Inventors: Ganesh Gopalasubramanian, Ashutosh Nema, Venugopal Raghavan
  • Automatic voltage reconfiguration
    Patent number: 11435806
    Abstract: Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 6, 2022
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Jerry A. Ahrens, Amitabh Mehra, Anil Harwani, William R. Alverson, Grant E. Ley, Charles Sy Lee
  • Automatic part testing
    Patent number: 11436114
    Abstract: Automatic part testing includes: booting a part under testing into a first operating environment; executing, via the first operating environment, one or more test patterns on the part; performing a comparison between one or more observed characteristics associated with the one or more test patterns and one or more expected characteristics; and modifying one or more operational parameters of a central processing unit of the part based on the comparison.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 6, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Amitabh Mehra, Anil Harwani, William R. Alverson, Grant E. Ley, Jerry A. Ahrens, Mustansir M. Pratapgarhwala, Scott E. Swanstrom
  • Method and apparatus for peer-to-peer messaging in heterogeneous machine clusters
    Patent number: 11429462
    Abstract: Various computing network messaging techniques and apparatus are disclosed. In one aspect, a method of computing is provided that includes executing a first thread and a second thread. A message is sent from the first thread to the second thread. The message includes a domain descriptor that identifies a first location of the first thread and a second location of the second thread.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Shuai Che
  • Buffer management for plug-in architectures in computation graph structures
    Patent number: 11431872
    Abstract: A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data when a last operation of the first group of operations executes.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Radhakrishna Giduthuri, Michael L. Schmit
  • Direct mapping mode for associative cache
    Patent number: 11422935
    Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 23, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien