Patents Assigned to Advanced Micro Devices, Inc.
  • Publication number: 20250111601
    Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatiotemporal adaptive sampling; performing a regularization operation based on an output of the shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250111587
    Abstract: Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Andrew Erin Kensler, Sean Keely, Michael John Livesley, David William John Pankratz
  • Publication number: 20250110655
    Abstract: Efficient memory operation using a destructive read memory array is described. In accordance with the described techniques, a system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jagadish B. Kotra, Divya Madapusi Srinivas Prasad
  • Publication number: 20250110878
    Abstract: Selectively bypassing cache directory lookups for processing-in-memory instructions is described. In one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. A processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the memory address. The cache directory bypass bit for a processing-in-memory request controls whether a cache directory lookup is performed after the processing-in-memory request is issued by a processor core and before the processing-in-memory request is executed by a processing-in-memory component.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Travis Henry Boraten, Jagadish B. Kotra, David Andrew Werner
  • Publication number: 20250112470
    Abstract: The disclosed device includes power circuits that can communicate with a control circuit. In response to a power circuit communicating a low efficiency state, the control circuit can redistribute at least a portion of a load of the power circuit to one or more other power circuits. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: David King Wai Li, Indrani Paul
  • Publication number: 20250110663
    Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jean J. Chittilappilly, Kevin M. Brandl, Jing Wang, Kedarnath Balakrishnan
  • Publication number: 20250111600
    Abstract: A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatially-adaptive sampling; performing a regularization operation based on an output of the sparse shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Guennadi Riguer, Michal Adam Wozniak
  • Publication number: 20250110525
    Abstract: A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Paul Blinzer, Maulik Ojas Mankad, Victor Ignatski, Ashish Jain, Gia Phan, Ranjeet Kumar
  • Publication number: 20250110664
    Abstract: A memory controller includes a command queue for receiving memory access requests and an arbiter. The arbiter is operable to allow cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses present in the command queue exceeding an adaptive threshold.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Guanhao Shen
  • Publication number: 20250110894
    Abstract: Scratchpad memory translation lookaside buffer techniques are described. In an implementation, the techniques described herein relate to a device including a memory management unit implemented in hardware of an integrated circuit to receive a mapping instruction from a mapping instruction source, the mapping instruction specifying a mapping between a virtual memory address and a physical memory address of a scratchpad memory and store a virtual-to-physical mapping entry in a translation lookaside buffer based on the mapping instruction.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Mark Evan Wilkening
  • Publication number: 20250111586
    Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael John Livesley, David William John Pankratz, Sean Keely, Andrew Erin Kensler
  • Publication number: 20250112389
    Abstract: A data interface connector and method of manufacture and/or assembly thereof can include first electrical terminals at a first end of the data interface connector, the first electrical terminals being configured to interface with a mating data interface connector conforming to a first data interface specification. The data interface connector and method of manufacture and/or assembly thereof can include second electrical terminals at a second end of the data interface connector, the second electrical terminals being configured to interface with data interface pads on a circuit board; where the data interface pads have pitches and lengths according to a second data interface specification.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: HaiFeng Gu
  • Publication number: 20250111006
    Abstract: Fast Fourier transforms for processing-in-memory are described. In accordance with the described techniques, a computing device includes a memory, a host processing unit, and a processing-in-memory unit that operates on data of one or more banks of the memory. The host processing unit stores interacting elements of a fast Fourier transform at locations in the one or more banks. The locations are mapped to a lane of the processing-in-memory unit. The host processing unit issues processing-in-memory commands instructing the processing-in-memory unit to load the interacting elements from the locations into the lane of the processing-in-memory unit, and execute an operation on the interacting elements.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mohamed Assem Abd ElMohsen Ibrahim, Shaizeen Dilawarhusen Aga
  • Publication number: 20250112047
    Abstract: A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Chandra Sekhar Mandalapu, Raja Swaminathan, Liwei Wang, John Wuu
  • Publication number: 20250110792
    Abstract: In accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. The host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. Further, the host processor submits the formatted task graph to a scalable input/output virtualization (SIOV) device, which directs the SIOV device to process the tasks of the task graph based on the order.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Stephen Alexander Zekany, Anthony Thomas Gutierrez
  • Publication number: 20250110864
    Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Anwar Parvez Kashem, Alicia Wen Ju Yurie Leong, Glennis Eliagh Covington
  • Publication number: 20250111195
    Abstract: Disclosed is a computer-implemented method for model ensemble acceleration in an active learning loop. The method includes receiving a set of datapoint inputs, where each datapoint input is an unlabeled equivalent of other datapoint inputs in the set of datapoint inputs and has a different applied weight value. The method then executes a set of neural network models, where the execution of each neural network model is based on the received set of datapoint inputs. The outputs from the set of neural network models are analyzed, where an inference computation is performed, and a label for the set of datapoints is determined. The method then stores the labeled set of datapoint inputs in a database. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Karthik Ramu Sangaiah, Yao Cui Fehlis
  • Publication number: 20250111585
    Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique includes for a subject node, selecting a dimension along which to perform a split to form child nodes of the subject node; assigning primitives of the subject node to the child nodes; and updating bounds for the child nodes in a next split dimension and not in the other dimensions.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Leo Hendrik Reyes Lozano
  • Patent number: 12266585
    Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: April 1, 2025
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
  • Patent number: 12265470
    Abstract: Selectively bypassing cache directory lookups for processing-in-memory instructions is described. In one example, a system maintains information describing a status—clean or dirty—of a memory address, where a dirty status indicates that the memory address is modified in a cache and thus different than the memory address as represented in system memory. A processing-in-memory request involving the memory address is assigned a cache directory bypass bit based on the status of the memory address. The cache directory bypass bit for a processing-in-memory request controls whether a cache directory lookup is performed after the processing-in-memory request is issued by a processor core and before the processing-in-memory request is executed by a processing-in-memory component.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: April 1, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Travis Henry Boraten, Jagadish B. Kotra, David Andrew Werner