Abstract: A memory controller includes a command queue having a first input for receiving memory access requests, and a memory interface queue having an output for coupling to a memory channel adapted for connecting to at least one dynamic random access memory (DRAM) module. A refresh control circuit monitors activate commands to be sent over the memory channel. In response to an activate command meeting a designated condition, the refresh control circuit identifies a candidate aggressor row associated with the activate command. A command is sent to the DRAM requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event.

Abstract: A processing device is provided which comprises memory and a processor. The processor is configured to receive an array of floating point numbers each having a plurality of bits used to represent a probability value. For each floating point number, the processor is configured to replace values in a portion of the bits used to represent the probability value with index values to represent an index corresponding to a location of a corresponding floating point number in the memory. The processor is also configured to process the floating point numbers using SIMD instructions to execute one of an argmax operation and an argmin operation.

Abstract: A host processor, such as a central processing unit (CPU), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (GPU), to provide motion compensation for encoded video. The motion compensation command for the plurality of cores of the massively parallel processor contains executable instructions for processing a plurality of motion vectors grouped by a plurality of prediction modes from a re-ordered motion vector buffer by the plurality of cores of the massively parallel processor.

Abstract: A system and method for providing security of sensitive information within chips using SIMD micro-architecture are described. A command processor within a parallel data processing unit, such as a graphics processing unit (GPU), schedules commands across multiple compute units based on state information. When the command processor determines a rescheduling condition is satisfied, it causes the overwriting of at least a portion of data stored in each of the one or more local memories used by the multiple compute units. The command processor also stores in the secure memory a copy of state information associated with a given group of commands and later checks it to ensure corruption by a malicious or careless program is prevented.

Abstract: Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.

Abstract: Disclosed herein are techniques for obtaining location data for a sensor fusion device. The techniques include transmitting or receiving a signal from or to the sensor fusion device. The techniques also include obtaining angle-based location data, based on the signal and on an angle-based location finding technique. The techniques also include determining location data for the sensor fusion device or an auxiliary device associated with the sensor fusion device, based on the angle-based location data.

Abstract: Described herein is a merged data path unit that has elements that are configurable to switch between different instruction types. The merged data path unit is a pipelined unit that has multiple stages. Between different stages lie multiplexor layers that are configurable to route data from functional blocks of a prior stage to a subsequent stage. The manner in which the multiplexor layers are configured for a particular stage is based on the instruction type executed at that stage. In some implementations, the functional blocks in different stages are also configurable by the control unit to change the operations performed. Further, in some implementations, the control unit has sideband storage that stores data that “skips stages.” An example of a merged data path used for performing a ray-triangle intersection test and a ray-box intersection test is also described herein.

Abstract: Systems, apparatuses, and methods for implementing a broadcast read response protocol are disclosed. A computing system includes a plurality of processing engines coupled to a memory subsystem. A first processing engine executes a read and broadcast response command, wherein the read and broadcast response command targets first data at a first address in the memory subsystem. One or more other processing engines execute a wait command to wait to receive the first data requested by the first processing engine. After receiving the first data from the memory subsystem, the plurality of processing engines process the first data as part of completing a first operation. In one implementation, the first operation is implementing a given layer of a machine learning model. In one implementation, the given layer is a convolutional layer of a neural network.

Abstract: An electronic device including a neural network processor and a presorter is described. The presorter determines a sorted order to be used by the neural network processor for processing a set of instances of input data through the neural network, the determining including rearranging an initial order of some or all of the instances of input data so that instances of input data having specified similarities among the some or all of the instances of input data are located nearer to one another in the sorted order. The presorter provides, to the neural network processor, the sorted order to be used for controlling an order in which instances of input data from among the set of instances of input data are processed through the neural network. A controller in the electronic device adjusts operation of the presorter based on efficiencies of the presorter and the neural network processor.

Abstract: Systems, apparatuses, and methods for enforcing processor quality of service guarantees when servicing system service requests (SSRs) are disclosed. A system includes a first processor executing an operating system and a second processor executing an application which generates SSRs for the first processor to service. The first processor monitors the number of cycles spent servicing SSRs over a previous time interval, and if this number of cycles is above a threshold, the first processor starts delaying the servicing of subsequent SSRs. In one implementation, if the previous delay was non-zero, the first processor increases the delay used in the servicing of subsequent SSRs. If the number of cycles is less than or equal to the threshold, then the first processor services SSRs without delay. As the delay is increased, the second processor begins to stall and its SSR generation rate falls, reducing the load on the first processor.

Abstract: An apparatus includes a plurality of registers to store sets of state information that represent a state history of a processing unit. The apparatus also includes a power management advisor (PMA) to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller including hardware circuitry that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.

Abstract: Systems, apparatuses, and methods for efficient parallel execution of multiple work units in a processor by reducing a number of memory accesses are disclosed. A computing system includes a processor core with a parallel data architecture. One or more of a software application and firmware implement matrix operations and support the broadcast of shared data to multiple compute units of the processor core. The application creates thread groups by matching compute kernels of the application with data items, and grouping the resulting work units into thread groups. The application assigns the thread groups to compute units based on detecting shared data among the compute units. Rather than send multiple read access to a memory subsystem for the shared data, a single access request is generated. The single access request includes information to identify the multiple compute units for receiving the shared data when broadcasted.

Abstract: Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket and a conductor layer. A chiplet is positioned in the pocket. The chiplet has plural bottom side interconnects electrically connected to the conductor layer and plural top side interconnects adapted to interconnect with two or more semiconductor chips.

Abstract: An apparatus includes an external device for causing messages to be transmitted with local traffic between internal blocks of a host system-on-chip (SoC) via a network on chip (NoC) in the host SoC, the transmitted messages including one or more memory requests directed to a memory of the host SoC, violating a traffic policy for a first time interval by transmitting a number of messages that exceeds a maximum threshold of for the first time interval, where the SoC monitors an amount of external traffic from an untrusted device transmitted over the NoC over a set of one or more time intervals including the first time interval, and in response to detection of the violation by the host SoC, reducing an amount of traffic transmitted via the NoC. The apparatus also includes an external processor link for transmitting the messages from the external device to the host SoC.

Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate quads. The quads are accumulated into a tile buffer. A shading rate is determined for the contents of the tile buffer. If the shading rate is a sub-sampling shading rate, then the quads in the tile buffer are down-sampled, which reduces the amount of work to be performed by a pixel shader. The shaded down-sampled quads are then restored to the resolution of the render target. If the shading rate is a super-sampling shading rate, then the quads in the tile buffer are up-sampled. The results of the shaded down-sampled or up-sampled quads are written to the render target.

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

Abstract: Techniques for generating a task graph for workload scheduling based on a task graph specification program are provided. The techniques include executing control flow instructions of the task graph specification program to traverse the task graph specification program; generating pass nodes of the task graph based on pass instructions of the task graph specification program; generating resource nodes and directed edges based on resource declarations of the task graph specification program; and outputting the task graph specification program to a command scheduler for scheduling.