Patents Assigned to Advanced Micro Devices, Inc.
  • Publication number: 20220147455
    Abstract: A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Kevin M. Lepak, William A. Moyes
  • Publication number: 20220148669
    Abstract: Methods, devices, and systems for testing a number of combinations of memory in a computer system. A modular memory device is installed in a memory channel in communication with a processor. The modular memory device includes a number of memory storage devices. The number of memory storage devices include a number of pins. For each of a number of subsets of the number of memory storage devices, a subset of the number of memory storage devices is selected, each pin of a subset of the number of pins which do not correspond to the subset of the number of memory storage devices is configured with a termination impedance, and the subset of the number of memory storage devices is tested.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Glennis Eliagh Covington, Benjamin Lyle Winston, Santha Kumar Parameswaran, Shannon T. Kesner
  • Publication number: 20220147366
    Abstract: In a system with a master processor and slave processors, sync points are used in boot instructions. While executing the boot instructions, the slave processor determines whether the sync point is enabled. In response to determining the sync point is enabled, the slave processor pauses execution of the boot instructions, waits for commands from the master processor, receives commands from the master processor, executes the received commands until a release command is received, and then continues to execute boot instructions. In response to determining the sync point is not enabled, the slave processor continues to execute boot instructions.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 12, 2022
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Wentao Xu, Randall Alexander Brown, Vaibhav Amarayya Hiremath, Shijie Che, Kamraan Nasim
  • Publication number: 20220147668
    Abstract: Techniques are disclosed for compressing data. The techniques include identifying, in data to be compressed, a first set of values, wherein the first set of values include a first number of two or more consecutive identical non-zero values; including, in compressed data, a first control value indicating the first number of non-zero values and a first data item corresponding to the consecutive identical non-zero values; identifying, in the data to be compressed, a second value having an exponent value included in a defined set of exponent values; including, in the compressed data, a second control value indicating the exponent value and a second data item corresponding to a portion of the second value other than the exponent value; and including, in the compressed data, a third control value indicating a third set of one or more consecutive zero values in the data to be compressed.
    Type: Application
    Filed: November 10, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Nicholas Malaya, Jakub Kurzak
  • Publication number: 20220141472
    Abstract: An encoding method is provided which includes receiving a plurality of images, obtaining values of elements in a portion of the images, sorting the elements according to different values of the elements, sorting the elements according to a number of occurrences of the different values and encoding the elements using a subset of the different values having corresponding numbers of occurrences that are higher than corresponding numbers of occurrences of other values. Examples also include a processing device and method for use with palette mode encoding in which the elements are a portion of pixels in images and the values are color values of the portion of pixels in the images.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Shu-Hsien Wu, Crystal Yeong-Pian Sau, Yang Liu, Wei Gao, Feng Pan, Ihab M. A. Amer, Ying Luo, Edward A. Harold, Gabor Sines, Ehsan Mirhadi
  • Patent number: 11321241
    Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish B. Kotra, Michael W. LeBeane
  • Patent number: 11321245
    Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 3, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul Moyer
  • Patent number: 11321903
    Abstract: A technique for performing ray tracing operations is provided. The technique includes receiving a ray for an intersection test, testing the ray against boxes specified in a bounding volume hierarchy to eliminate one or more boxes or triangles from consideration, unpacking a triangle from a compressed triangle block of the bounding volume hierarchy, the compressed triangle block including two or more triangles that share at least one vertex, and testing the ray for intersection against at least one of the unpacked triangles.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 3, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Young In Yeo
  • Patent number: 11315883
    Abstract: An apparatus includes a substrate including an identification code on a first side of the substrate and near a perimeter of the substrate. The apparatus includes a stiffener structure attached to the first side of the substrate. The stiffener structure has a cutout in an outer perimeter of the stiffener structure. The stiffener structure is oriented with respect to the substrate to cause the cutout to expose the identification code. The cutout may have a first dimension and a second dimension orthogonal to the first dimension. The first dimension may exceed a corresponding first dimension of the identification code and the second dimension may exceed a corresponding second dimension of the identification code, thereby forming a void region between the identification code and edges of the stiffener structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 26, 2022
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Suming Hu, Roden Topacio, Farshad Ghahghahi, Jianguo Li, Andrew Kwan Wai Leung
  • Patent number: 11314646
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Publication number: 20220122652
    Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
    Type: Application
    Filed: December 29, 2021
    Publication date: April 21, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Patent number: 11308057
    Abstract: Described herein is a system and method for multiplexer tree (muxtree) indexing. Muxtree indexing performs hashing and row reduction in parallel by use of each select bit only once in a particular path of the muxtree. The muxtree indexing generates a different final index as compared to conventional hashed indexing but still results in a fair hash, where all table entries get used with equal distribution with uniformly random selects.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 19, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven R. Havlir, Patrick J. Shyvers
  • Patent number: 11307993
    Abstract: For one or more stages of execution of a software application at a first processor, a remap vector of a second processor is reconfigured to represent a dynamic mapping of virtual address groups to physical address groups for that stage. Each bit position of the remap vector is configured to store a value indicating whether a corresponding virtual address group is actively mapped to a corresponding physical address group. Address translation operations issued during a stage of execution of the software application are selectively processed based on the configuration of the remap vector for that stage, with the particular value at the bit position of the remap vector associated with the corresponding virtual address group controlling whether processing of the address translation operation is continued to obtain a virtual-to-physical address translation sought by the address translation operation or processing of the address translation operation is ceased and a fault is issued.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 19, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Anthony Asaro, Richard E. George
  • Patent number: 11309222
    Abstract: Various semiconductor chips with solder capped probe test pads are disclosed. In accordance with one aspect of the present invention, a semiconductor chip is provided that includes a substrate, plural input/output (I/O) structures on the substrate and plural test pads on the substrate. Each of the test pads includes a first conductor pad and a first solder cap on the first conductor pad.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 19, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Lei Fu, Milind S. Bhagavat, Chia-Hao Cheng
  • Patent number: 11309911
    Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 19, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
  • Patent number: 11307631
    Abstract: A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 19, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Vedula Venkata Srikant Bharadwaj
  • Patent number: 11308648
    Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: April 19, 2022
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Saurabh Sharma, Laurent Lefebvre, Sagar Shankar Bhandare, Ruijin Wu
  • Publication number: 20220114097
    Abstract: Methods, devices, and systems for managing performance of a processor having multiple compute units. An effective number of the multiple compute units may be determined to designate as having priority. On a condition that the effective number is nonzero, the effective number of the multiple compute units may each be designated as a priority compute unit. Priority compute units may have access to a shared cache whereas non-priority compute units may not. Workgroups may be preferentially dispatched to priority compute units. Memory access requests from priority compute units may be served ahead of requests from non-priority compute units.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Zhe Wang, Sooraj Puthoor, Bradford M. Beckmann
  • Patent number: 11301256
    Abstract: Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 12, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lisa R. Hsu, James Michael O'Connor
  • Patent number: 11294810
    Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 5, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William L. Walker, William E. Jones