Abstract: A method for constructing a global interconnect model of a device having ambiguous abutments between submodules includes generating a discrete model for each of the submodules, identifying interconnections between the submodules, and defining a plurality of global abutment points for the interconnections between the submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of a boundary of a particular one of the submodules. The discrete models are stitched together based on the global abutment points to construct a global model.

Abstract: A system that monitors and controls a phase shift mask fabrication process is disclosed. Acoustic beams and/or beams of light are selectively directed at portions of the mask to scan the mask as it matriculates through the fabrication process. Portions of the beams that pass through and/or are reflected from the mask are collected and examined, such as in accordance with scatterometry based techniques, to determine, for example, whether cracks or other defects are forming on or within the mask, and/or whether features, such as apertures, are being formed as desired. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Controlling the mask fabrication process facilitates improved mask fabrication and resulting chip quality as compared to conventional systems.

Abstract: A novel physical layer transceiver is provided for receiving data transmitted via residential wiring. The transceiver includes an input circuit for receiving an incoming pulse signal, and an energy detector responsive to the incoming pulse signal for producing a pulse energy value representing energy of the incoming pulse signal. An adaptive energy detector gain control circuit is responsive to the pulse energy value for adaptively controlling gain of the energy detector so as to maintain the pulse energy value at a predetermined level. The gain of the energy detector is controlled in response to at least one of access identification pulses preceding data pulses to identify the transmitting station. The adaptive energy detector gain control circuit includes a comparator for comparing a pulse energy value produced by the energy detector with a preset threshold level, and a controller for supplying the energy detector with a gain control value.

Abstract: The present invention is generally directed to various control methodologies using optical emission spectroscopy derived data, and a system for performing same. In one illustrative embodiment, the method comprises performing an etching process within an etch tool to define at least one feature above a semiconducting substrate, obtaining optical emission spectroscopy data for the etching process, and controlling at least one parameter of the etching process based upon a comparison of the obtained optical emission spectroscopy data and target optical emission spectroscopy data associated with at least one of a target profile and a target critical dimension for the at least one feature.

Abstract: A starvation avoidance mechanism for an input/output node of a computer system. A scheduler unit includes a first buffer circuit and a second buffer circuit. The first buffer circuit includes a first plurality of buffers for storing selected control commands received from a first source and the second buffer circuit includes a second plurality of buffers for storing selected control commands received from a second source. The scheduler further includes an arbitration circuit coupled to the first buffer circuit and to the second buffer circuit. The arbitration circuit may be configured to arbitrate between the control commands stored in the first buffer circuit and the control commands stored in the second buffer circuit. The outcome of selected arbitration cycles may be dependent upon a number of times in which a control command from a given one of the buffers is blocked due to an unavailable destination.

Abstract: A method of determining the active region width (10) of an active region (4) by measuring the respective capacitance values (C100, C100′, C100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element(16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective capacitance values (C100, C100′, C100″) as a quasi-linear function (CW) of the respective predetermined widths (Wi), extrapolating a calibration term (WC=0) from the quasi-linear function (CW), and subtracting the calibration term (WC=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.

Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved and hillock formation is significantly reduced by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of trimethylsilane and then initiating deposition of a silicon carbide capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, shutting off the power, discontinuing the N2 flow and introducing He, then ramping up the introduction of trimethylsilane in three stages, and then initiating plasma enhanced chemical vapor deposition of a silicon carbide capping layer, while maintaining substantially the same temperature of 335° C. throughout plasma treatment and silicon carbide capping layer deposition. Embodiments also include forming Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than 3.9.

Abstract: A system and method is provided that facilitates the uniform development of a pattern on a photoresist material layer using a developer. The present invention accomplishes this end by considering the acid-base relationship of the photoresist material and developer and monitoring the development of water formed in the development process. Typically, photoresist material is purchased or manufactured with known concentrations of resin and photoacid generator. Therefore, by monitoring the development of water in the development process, the present invention can measure the acid consumption in the development process. The present invention can then utilize this information in optimizing the developer volume, developer concentration and developer time to improve the quality of the developed image pattern on the photoresist material layer.

Abstract: A method of removing organic anti-reflective coating (ARC) by ashing in an integrated circuit fabrication process can include providing an oxide-nitride-oxide (ONO) stack over a silicon substrate, providing a poly layer over the ONO stack, and patterning spaces in the poly layer using a patterned carbon bilayer ARC layer and a patterned hardmask layer. The patterned carbon bilayer ARC layer is ashed away before patterning spaces in the poly layer. Ashing the carbon bilayer ARC layer helps prevent damage to the ONO stack, improving the quality of the fabricated device.

Abstract: A sense amplifier circuit. Specifically, a sample and hold sense amplifier circuit that is capable of sampling and holding a reference voltage comprises a reference voltage sampler circuit coupled to a cross-coupled inverter latch. The reference voltage sampler circuit is coupled to a bitline associated with a memory cell. The reference voltage is sampled from a precharge voltage taken off the bitline, and is used to read a state on a memory cell. The cross-coupled inverter latch is also coupled to the bitline, and is used for amplifying a voltage difference between an output voltage from the cross-coupled inverter latch and the reference voltage. The output voltage is based on a static bitline voltage from the bitline.

Abstract: A method is provided, the method comprising measuring at least one parameter characteristic of rapid thermal processing performed on a workpiece in a rapid thermal processing step, and modeling the at least one characteristic parameter measured using a first-principles radiation model. The method also comprises applying the first-principles radiation model to modify the rapid thermal processing performed in the rapid thermal processing step.

Abstract: A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.

Abstract: An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 &mgr;m, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.

Abstract: A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

Abstract: An apparatus for obtaining information on critical dimensions and overlay accuracy of features in a semiconductor structure comprises a light source, a detector and an optical means defining a first optical path and a second optical path. The first optical path and the second optical path are oriented in correspondence with the respective orientations of diffracting patterns provided on the semiconductor structure to obtain the required information without the necessity of rotating the semiconductor structure. This insures a significantly higher throughput.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for controlling supply process gas to a process chamber for use in the manufacturing industry. Methods include controlling the operation of a valve coupled to the supply process gas line in a way such that pressure bursts in the process chamber due to the operation of the valve are reduced, or even eliminated.

Abstract: The present invention is generally directed to various methods of controlling the formation of metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and measuring at least one characteristic of at least one metal silicide region while the anneal process is being performed. In another illustrative embodiment, the method comprises forming a layer of refractory metal above a feature, performing at least one anneal process to convert a portion of the layer of refractory metal to at least one metal silicide region on the feature, and performing at least one scatterometric measurement of the metal silicide region after at least a portion of the anneal process is performed to determine at least one characteristic of the metal silicide region.

Abstract: An arrangement for testing flow control logic in a network device such as a network switch includes a traffic generator configured for transmitting pause frames having prescribed pause values. The network device is configured for continuously transmitting data frames on a network medium. The traffic generator is configured for outputting a first pause frame to the network device that specifies a first pause interval on the order of ten minutes, followed by outputting during the first pause interval a second pause frame specifying a second pause interval substantially less than the first pause interval, for example on the order of ten seconds. The traffic generator is configured for measuring a time interval between transmission of the first pause frame and reception of subsequent data frames from the network device for evaluation of the flow control logic. Hence, the traffic generator can determine whether the second pause frame causes the flow control logic to cancel the first pause frame.

Abstract: Substrate removal for analysis of a semiconductor die is enhanced via a method and system for heating the die. According to an example embodiment of the present invention, a plurality of heating elements are formed in a semiconductor die. The die is operated while at least one of the plurality of heating elements heats a portion of the die adjacent the heating element. A response to the heating is detected and used to analyze the die. The present invention makes possible selective heating of the die in a manner that is readily controllable and implemented. Die analysis, including, for example, critical timing path analysis, is enhanced by this ability to controllably heat the die.

Abstract: A system for processing tester information is provided. Data is collected for a plurality of dies on a semiconductor wafer. Data and a pattern covering the semiconductor wafer are selected. Selected data are graphed in a trellis of graphs spread across the semiconductor wafer. The trellis of graphs is oriented over an outline of the semiconductor wafer.