Abstract: A semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the multiple parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias extending to the gate electrode line and the source/drain regions. A method of manufacturing the semiconductor device is also disclosed.

Abstract: A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode, at least one of sidewall/spacers, second sidewalls or a barrier layer, in which the floating gate is positioned above the channel region. The floating gate may be separated from the channel region by one or more of a reverse tunnel dielectric layer, the barrier layer and a pad dielectric layer. The floating gate may be a metal floating gate.

Abstract: Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate architecture. The dopant is provided by a tilt angle around the existing floating gate/control gate structure at the stage of the fabrication process where the floating gate/control structure is in existence, the field oxidation step may also have occurred, and implantation of the source and drain dopants may also have occurred. This forms a retrograde n-type distribution away from the direction of the surface of the substrate in the channel, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This deposition promotes buried-channel-like performance of the NMOS transistors connected in series in the NAND gate memory architecture.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: In a method and system for transferring data between a plurality of bus devices, a bus interface unit includes a first bus device interface (FBDI), a second bus device interface (SBDI), and an arbitration circuit. Each of the FBDI and SBDI includes a corresponding incoming and outgoing request bus for receiving and transmitting request packets from a corresponding one of the plurality of bus devices. Similarly, each of the EBDI and SBDI also includes a corresponding incoming and outgoing data bus for receiving and transmitting data packets from the corresponding one of the plurality of bus devices. The arbitration circuit is capable of determining priority level associated with corresponding request packets received from the FBDI and the SBDI respectively.

Abstract: The source resistance of a MOSFET is determined by grounding the source and applying a voltage to the substrate to force a current Isub-S through the source. The gate and drain are allowed to float while the current is forced. Since no current flows between the source and drain, a voltage VDS detected at the drain is the product of the forced current Isub-S and the source resistance RS. Accordingly, the source resistance RS is determined to be the drain voltage VDS divided by the forced current Isub-S. Drain resistance RD may be measured in an analogous manner.

Abstract: Patterned layers in an integrated circuit (IC) or other device are aligned in conjunction with the detection of the topology of the layers. The topology can be used to determine the location of a metrology mark and/or to compensate for a horizontal shift in the apparent location of the metrology mark. Precise detection of topography can be achieved without physical contact with the IC or other device with an atomic force microscope.

Abstract: Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.

Abstract: A network switch configured for switching data packets across multiple ports uses decision making logic to generate frame forwarding information. The decision making logic employs a pipelined architecture that enables multiple data frames to be processed simultaneously to increase data throughput. The decision making logic also pipelines access to an address lookup table that stores the data forwarding information. An arbitration circuit provides the decision making device with automatic access to the address table in alternate time slots and also enables other circuits to access the address table in predetermined time slots.

Abstract: A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer are tuned by forming differing patterns in a plurality of the partial die areas.

Abstract: A fabrication system utilizes a protocol for removing native oxide from a top surface of a wafer. An exposure to a plasma, such as a plasma containing hydrogen and argon can remove the native oxide from the top surface without causing excessive germanium contamination. The protocol can use a hydrogen fluoride dip. The hydrogen fluoride dip can be used before the plasma is used. The protocol allows better silicidation in SMOS devices.

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract: One aspect of the present invention relates to a system and method for mitigating LER as it may occur on short wavelength photoresists. The method involves forming a short wavelength photoresist over a substrate having at least one dielectric layer formed thereon, exposing the photoresist to a plasma selective to the photoresist to strengthen the photoresist without substantially etching the at least one dielectric layer, the plasma comprising hydrogen, helium and argon, and etching the dielectric layer through openings of the strengthened photoresist with an etchant selective to the at least one dielectric layer, whereby the treated photoresist is substantially resistant to etching effects of the etchant. The system includes a photoresist monitor system for monitoring the plasma treatment to determine whether the photoresist has been strengthened and for adjusting parameters associated with the plasma treatment and for providing feedback to the plasma treatment system.

Abstract: The network interface device has multiple blocks having internal connections, and has an external interface. The network interface device is configurable to reroute one or more of the internal connections onto the external interface to allow testing of the blocks of the device. The external interface may also be coupled so as to pass data between the network interface device and higher levels in a network protocol stack. In an exemplary embodiment a network interface device has a media access controller (MAC) and a physical layer device (PHY). An internal media independent interface (MII) between the MAC and the PHY may be selectively rerouted to an external MII for independently testing operation of either the MAC or the PHY.

Abstract: A method of determining charge loss activation for a memory array. Memory arrays are programmed with a pattern for testing charge loss. Then, respective bake times are calculated for the memory arrays to experience a given amount of charge loss at their respective bake temperatures. Then, charge loss activation energy is calculated, based on the respective bake times. In one version, the memory arrays are cycled by repeatedly erasing and reprogramming them before baking. In another embodiment, various regions of the memory arrays are programmed to a plurality of distinct delta threshold voltages before baking.

Abstract: An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

Abstract: A space-saving test structure includes a core metal line, at least one extrusion detection line and an extrusion monitoring segment. The core metal line has a “non-linear configuration” and is capable of conducting current for an electromigration test, an isothermal test, and extrusion monitoring. The at least one extrusion detection line is situated adjacent to the core metal line. The extrusion monitoring segment is electrically connected to the at least one extrusion detection line. The extrusion monitoring segment is adapted to determine whether an extrusion occurs in the core metal line by measuring a resistance between the core metal line and the at least one extrusion detection line.

Abstract: A system and method are disclosed which enable temperature of a substrate, such as mask or reticle, to be monitored and/or regulated. One or more temperature sensors are associated with the substrate to sense substrate temperature during exposure by an exposing source. The sensed temperature is used to control one or more process parameters of the exposure to help maintain the substrate at or below a desired temperature.

Abstract: A manufacturing process for fabricating field effect transistors is disclosed comprising the generation of a strained surface layer on the surface of the substrate on which the transistor is to be fabricated. The strained surface layer is generated by implanting xenon and/or other heavy inert ions into the substrate. Implantation can be performed both after or prior to the gate oxide growth. The processing afterwards is carried out as in conventional MOS technologies. It is assumed that the strained surface layer improves the channel mobility of the transistor.

Abstract: A method and an apparatus for dynamic targeting for a process control system. Inline parameter data relating to a processed workpiece is received. A determination is made whether the inline parameter would result in a value of a device operation parameter within a predetermined range. At least one process operation performed upon the workpiece is adjusted in response to a determination that the inline parameter would not result in a value of the device operation parameter.