Abstract: A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

Abstract: A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter.

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, introducing dopants into the substrate, forming a tuning layer over at least a portion of the substrate, and activating the dopants using laser thermal annealing. The tuning layer causes an increase or a decrease in the amount of fluence absorbed by the portion of substrate below the tuning layer in comparison to an amount of fluence absorbed by a portion of substrate not covered by the tuning layer. Additional tuning layers can also be formed over the substrate.

Abstract: A method of programming a memory cell that has 2N voltage levels where N>1 and represents the number of bits stored within the memory cell. The method includes generating a first programming pulse, generating a second programming pulse subsequent to the generating the first programming pulse, wherein the first programming pulse has a width that is greater than the second programming pulse and programming at least two of the 2N voltage levels with the first programming pulse.

Abstract: A burn-in board and a method for thermally testing the burn-in board determines if the burn-in board is defective. The burn-in board includes components on a front side of the burn-in board and thermal tape on the back side of the burn-in board. Power and ground are supplied to the burn-in board and the thermal tape changes color indicating a hot spot if the burn-in board contains one or more problem areas.

Abstract: Channel carrier mobility is increased by reducing gate/gate dielectric interface roughness, thereby reducing surface scattering. Embodiments include depositing a layer of silicon by selective epitaxy prior to gate oxide formation to provide a substantially atomically smooth surface resulting in a smoother interface between the gate polysilicon and silicon oxide after oxidation.

Abstract: A method utilizing a multilayer anti-reflective coating layer structure. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating.

Abstract: A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

Abstract: A processor employing a dependency link file. Upon detection of a load which hits a store for which store data is not available, the processor allocates an entry within the dependency link file for the load. The entry stores a load identifier identifying the load and a store data identifier identifying a source of the store data. The dependency link file monitors results generated by execution units within the processor to detect the store data being provided. The dependency link file then causes the store data to be forwarded as the load data in response to detecting that the store data is provided. The latency from store data being provided to the load data being forwarded may thereby be minimized. Particularly, the load data may be forwarded without requiring that the load memory operation be scheduled.

Abstract: The present invention provides for a method and an apparatus for controlling multiple semiconductor wafer cups. At least one process run of semiconductor devices is processed. A multi-wafer-cup process analysis is performed upon the processed semiconductor devices. At least one control parameter is modified for a subsequent process run of semiconductor devices using results from the multi-wafer-cup process analysis.

Abstract: A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device.

Abstract: A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

Abstract: A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.

Abstract: A microcontroller has many miscellaneous logics. The miscellaneous logic can include input/outputs of combinational logic or peripheral devices of the microcontroller, storage devices such as latches, or registers. The miscellaneous logic is coupled to multiple stages of scan cells. The multiple stages can be used as a buffer while the last stage of scan cells are scanned out. A predetermined stage of scan cells are coupled together to form a scan path where data from the miscellaneous logic can be outputted to an external memory. In one embodiment, the predetermined stage is the last stage of scan cells. A trigger signal is used to shift the data from the miscellaneous logic to the next stage of scan cells. Once the last stage of scan cells are loaded, a clocking signal can be provided so that the data in the predetermined stage of scan cells is scanned out. The present invention provides among other things, a graceful way to capture data from miscellaneous logic of the microcontroller using scan hardware.

Abstract: A new device and technique to realize an improved integrated circuit device incorporates an improved polysilicon upper surface. This improvement is achieved by approximately planarizing an upper surface of the polysilicon layer. First, the polysilicon layer is preferably formed as a relatively thicker layer as compared to the layer thickness in a conventional device. Then a portion of the polysilicon layer is removed, preferably utilizing a chemical mechanical polish technique. Thus, this embodiment achieves a relatively planarized upper surface of the polysilicon layer. Then, for example, a conventional metal or silicide layer may be formed upon the relatively planarized polysilicon layer. This approximately planarized upper surface of the polysilicon layer allows for a silicide layer to be formed with a relative reduction in the amount and/or severity of the conventional word line voids and seams.

Abstract: A system and method that operate on data in a communication system. The system comprises a communication network for routing objects that include data and a tag and comprised of processing modules for processing the data included in the objects and routing nodes that are operable to route the objects between the processing modules. Each processing module includes a processing memory for storing objects. Each routing node includes a routing memory for storing memory objects and is operable to route objects throughout the system. The objects include stored objects stored in various ones of the respective processing memories and the respective routing memories. Each stored object further includes methods that are executable to perform operations on the data and a processing list that lists the methods to be executed on the data. Each processing node interrogates objects to examine the processing list and execute methods identified by the processing list to perform corresponding operations on the data.

Abstract: An apparatus is provided wherein a substrate is mechanically clamped to a heater block of a die bonder to hold down the heated substrate before and during the die bonding operation, thereby preventing warpage of the substrate. Embodiments include a clamp comprising a plurality of spring-loaded rollers which push down opposing outer edges of the substrate onto the heater block while the substrate is being heated and die bonded. The clamp minimizes warpage of the substrate by pushing the substrate flat onto the heater block, and allows the substrate to be moved into and away from the die bonding area.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by forming a relatively thick silicon oxide liner on the side surfaces of the gate electrode and adjacent surface of the semiconductor substrate before forming the silicon nitride sidewall spacers thereon. Embodiments include forming a silicon dioxide liner at a thickness of about 200 Å to about 600 Å prior to forming the silicon nitride sidewall spacers thereon.

Abstract: An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using a negative gate erase voltage during an erase procedure to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. During the erase procedure, an erase cycle is applied followed by a read cycle until the cell has a threshold erased below a desired value. For the initial erase cycle in the procedure, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the threshold is reduced below the desired value. In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when the erase procedure is again applied, the initial negative gate voltage applied is the negative gate voltage value for the cell stored in memory.