Abstract: A computer system automatically determines and displays the physical location of a failed memory cell of an array of memory cells on magnified images of a memory IC (integrated circuit) die from label information of the failed memory cell generated by a test station. The label information includes any combination of a sector label, an I/O label, a column label, and a row label. The memory IC die is comprised of a plurality of sectors, and the sector label corresponds to the sector having the failed memory cell located therein. A sector is comprised of a plurality of I/O regions, and the I/O label specifies the I/O region having the failed memory cell located therein, within the sector having the sector label. An I/O region is comprised of a plurality of horizontal conductive structures and vertical conductive structures.

Abstract: A semiconductor device and a method of making the semiconductor device having a composite dielectric layer including steps of providing a semiconductor substrate; depositing on the semiconductor substrate alternating sub-layers of a first dielectric material and a second dielectric material to form a layered dielectric structure having at least two sub-layers of at least one of the first dielectric material and the second dielectric material, wherein one of the first dielectric material and the second dielectric material is a high-K. dielectric material and an other of the first dielectric material and the second dielectric material is a standard-K dielectric material; and annealing the layered dielectric structure at an elevated temperature to form a composite dielectric layer.

Abstract: For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on a portion of the active device area. First spacers are formed on sidewalls of the gate electrode and the gate dielectric. A contact dopant is implanted into exposed regions of the active device area to form drain and source contact junctions. A contact laser thermal anneal is performed to activate the contact dopant within the drain and source contact junctions. The first spacers are removed, and an extension dopant is implanted into exposed regions of the active device area to form drain and source extension junctions. An extension laser thermal anneal is performed to activate the extension dopant within the drain and source extension junctions. The fluence of the extension laser thermal anneal is lower than the fluence of the contact laser thermal anneal.

Abstract: A method of using amorphous carbon as spacer material in a disposable spacer process can include forming amorphous carbon spacers at lateral side walls of a gate structure over a substrate, implanting dopants in the substrate to form source and drain regions, ashing away the amorphous carbon spacers, and implanting dopants to form shallow structures in the substrate.

Abstract: The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.

Abstract: A system and method are disclosed for measuring and/or imaging a feature having a re-entrant cross-sectional profile. Beams are emitted onto the feature and substrate at different angles during corresponding measurement intervals. An feature data set of the feature is characterized for each measurement interval. The data associated with each measurement interval are aggregated to provide a cross-sectional representation of the having dimensions proportional to the feature. As a result, a more accurate feature profile may be determined, including a cross-sectional dimension of the re-entrant feature at the juncture between the feature and substrate.

Abstract: In general, the present invention is directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method comprises forming a layer of titanium nitride by a chemical vapor deposition process, sensing a thickness of the layer of titanium nitride, and providing the sensed thickness of the layer of titanium nitride to a controller. The method further comprises determining at least one parameter of a plasma process to be performed on the layer of titanium nitride based upon the sensed thickness of the layer of titanium nitride and performing the plasma process comprised of the determined at least one parameter on the layer of titanium nitride.

Abstract: A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks accesses to the system registers. Each resource change register is coupled to a bit in a summary register. For systems with numerous system registers, each summary register may be coupled to a bit in a higher-level summary register. The register change summary resource further provides a software-controlled bit mask register. A change in a summary or resource change register may trigger a processor interrupt. Each register in the register change summary resource can be reset, also under software control. The registers within the register change summary resource are accessible through a dedicated software development port.

Abstract: An apparatus and method are presented for programmable built-in self-test (BIST) and built-in self-repair (BISR) of an embedded memory (i.e., a memory formed with random logic upon a semiconductor substrate). A semiconductor device may include a memory unit, a BIST logic unit coupled to the memory unit, and a master test unit coupled to the BIST logic unit and the memory unit. The memory unit stores data input signals in response to a first set of address and control signals, and provides the stored data input signals as data output signals in response to a second set of address and control signals. The master test unit provides the memory test pattern to the BIST logic unit and generates the first and second sets of address and control signals.

Abstract: A novel method is provided for dynamically programming a programmable logic device (PLD). The method involves programming a required test pattern into the PLD using a programming pulse signal having the minimum pulse width. Then, the PLD programming is verified. If the PLD programming is found to be improper, the pulse width of the programming pulse signal is automatically adjusted to a normal pulse width greater than the minimum pulse width. Thereafter, the required test pattern is again programmed into the PLD using the programming pulse signal having the normal pulse width.

Abstract: A method and system for improving memory access in Accelerated Graphics Port systems. The method and system associate a transaction id with individual data transactions within a number of Accelerated Graphics Port (AGP) pipelined data transactions, and identify the individual data transactions within the number of AGP pipelined data transactions via the transaction id. In one instance, the association of a transaction id with individual data transactions includes but is not limited to associating a transaction id with each individual memory read request within a number of AGP pipelined memory read requests and associating an identical transaction id with each individual data unit, within a number of pipelined data units, corresponding to each individual memory read request within the number of AGP pipelined memory requests.

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.

Abstract: The present invention provides for a method and an apparatus for reducing the effects of manufacturing environmental factors. At least one process run of semiconductor devices is processed. A manufacturing environmental data analysis is performed upon the process run of semiconductor devices. A control parameter modification sequence is implemented in response to the manufacturing environmental data analysis.

Abstract: A processor supports an operating mode in which the default address size is greater than 32 bits and the default operand size is 32 bits. The default address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the operating mode. The operating mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Additionally, a first instruction prefix may be coded into an instruction to override the default operand size to a first non-default operand size (e.g. 64 bits). Furthermore, a second instruction prefix may be coded into an instruction in addition to the first instruction prefix to override the default operand size to a second non-default operand size (e.g. 16 bits).

Abstract: For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material.

Abstract: A system-on-a-chip with a variable clock rate bus. The integrated circuit includes at least one bus, a clock, a plurality of modules coupled to the bus and operable to transfer and receive data on the bus, and a bus controller coupled to the bus that controls data transfers on the bus. The modules are operable to generate requests to the bus controller to perform transfers on the bus. Each request comprises an identifier which identifies one or more receiving modules, a transfer size value which specifies the amount of data to be transferred, and a timing value providing a time frame within which the requested data transfer should occur. Thee bus controller receives the requests, analyzes the timing value, and selectively adjusts the clock rate of the bus based on the timing value.

Abstract: A method is provided for manufacturing, the method including processing a workpiece in a processing step, detecting defect data after the processing of the workpiece in the processing step has begun and forming an output signal corresponding to at least one type of defect based on the defect data. The method also includes feeding back a control signal based on the output signal to adjust the processing performed in the processing step to reduce the at least one type of defect.

Abstract: A method and system for improving virtual memory performance, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. In the method and system, a request to access a first virtual memory address, correspondent to a first physical memory location resident within a first page of physical memory, is received. In response to the request to access the first virtual memory address, a Graphics Translation Look Aside Buffer entry is created. In response to a request to access a second virtual memory address, correspondent to a second physical memory address resident within a second physical memory area non-overlapping with the first physical memory page, the second physical memory location is accessed via the Graphics Translation Look Aside Buffer entry. The Graphics Translation Look Aside Buffer entry is constructed such that it translates a number of virtual memory addresses corresponding to a number of physical memory addresses.

Abstract: The method as disclosed reduces the topological step between the uppermost surface of a substrate and the uppermost surface of a shallow trench isolation feature. The method includes the steps of forming a pad oxide layer overlying a substrate, forming a stop layer overlying the pad oxide layer, forming a second oxide layer overlying the stop layer, forming a patterning layer overlying the second oxide layer, and patterning the patterning layer and underlying stack to form an exposed portion of the substrate. The exposed portion of substrate is etched to form a trench, and the remaining portion of the oxidation resistant layer is removed. Further, a dielectric layer is formed overlying the remaining portion of the second oxide layer, and filling the trench. A portion of the dielectric layer is removed to leave the top of the dielectric layer substantially level with the stop layer, and then the stop layer is removed.

Abstract: A computing system employs an unicode driver to access and control peripheral devices by abstracting commands and status data to a level above register sets of similar but potentially incompatible peripheral devices. A unicode may be generated by an operating system or the unicode driver. Unicodes are routed by a device configuration interface that passes the unicodes between the unicode driver and peripheral devices. The peripheral devices include command decoders for performing conversion between unicodes and device-specific instructions. The use of unicode drivers eliminates duplicate driver code and simplifies device configuration for the computing system.