Abstract: A thermal test chip array and method of forming the same allows access to any test die in the array regardless of the size of the array. The thermal test chip arrangement has a plurality of thermal test chips arranged in an array, each thermal test chip having a heating circuit and a temperature-sensing circuit. A first set of conductive lines traverse unbroken across the entire array. The heating circuit of each thermal test chip is connected to some of the first set of conductive lines. These conductive lines provide power to the heating circuits of the thermal test chips. A second set of conductive lines traverse unbroken across the entire array with the temperature-sensing circuit of each thermal test chip being connected to some of the second set of conductive lines. Power is carried to the temperature sensing circuits of the thermal test chips by the second set of conductive lines.

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate, forming source/drain extensions in the substrate, and forming first and second sidewall spacers. Dopants are then implanted within the substrate to form amorphitized source/drain regions in the substrate adjacent to the sidewalls spacers. The amorphitized source/drain regions are partially recrystallized, and laser thermal annealing activates the source/drain regions. The source/drain extensions and sidewall spacers are adjacent to the gate electrode. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. Also, the recrystallization reduces the amorphitized source/drain regions by a depth of about 20 to 100 angstroms. A semiconductor device is also disclosed.

Abstract: Provided herein is a method of utilizing electroless copper deposition to form interconnects in a semiconductor device. An opening is formed in a dielectric layer in the form of a trench, via or combination thereof, and a diffusion barrier layer is blanket deposited in the opening. Then, a contact displacement technique is used to form a seed layer on the diffusion barrier layer which includes copper, tin and palladium. Electroless deposition of copper is been undertaken to autocatalytically deposit copper on the activated barrier layer. The process continues to create a conformal, void free electroless copper deposition.

Abstract: The present invention provides for a method and an apparatus for interfacing a statistical process control system with a manufacturing control system. A manufacturing model is defined. A processing run of semiconductor devices is processed in a manufacturing facility as defined by the manufacturing model. An advanced process control analysis is performed on the processed semiconductor devices. A statistical process control analysis is performed on the processed semiconductor devices. The manufacturing facility is modified in response to the advanced process control analysis and the statistical process control analysis.

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand.

Abstract: A method for forming a conductive interconnect comprises forming a process layer over a structure layer and forming a mask over the process layer, the mask having an etch profile therein. An anisotropic etching process is performed to erode the mask and to form an etched region in the process layer, the etched region having a profile correlating to the etch profile. A conductive material is formed in the etched region in the process layer and any excess conductive material is removed from above an upper surface of the process layer.

Abstract: An integrated circuit, system and method monitors parameter performance for optimization of controller performance. The integrated circuit includes a memory controller, one or more buffers coupled to the memory controller, and a performance monitoring circuit coupled to the one or more buffers and an SDRAM controller, the performance monitoring circuit to receive at least one parameter related to the buffers and provide statistical data related to the parameter. The statistical data may be used to set an amount of data to accumulate in the one or more buffers. A method includes transmitting one or more parameters related to performance of one more components of an integrated circuit to a performance monitoring circuit located within the integrated circuit. The performance monitoring circuit then determines statistical data related to the parameter independent of an interrupt to the integrated circuit.

Abstract: A barrier layer can be provided over a photoresist film to prevent outgassing. The barrier layer can be relatively highly transmissive to radiation at the actinic wavelength. The barrier layer can be removed before the photoresist layer is developed.

Abstract: In general, the present invention is directed to acoustically enhanced deposition processes, and a system for performing same. In one embodiment, the method comprises providing a substrate having a layer of insulating material formed thereabove, the layer of insulating material having a plurality of openings formed therein, performing a deposition process to form a layer of metal at least in the openings in the layer of insulating material, and actuating at least one acoustic generator to generate sound waves during the deposition process. In one illustrative embodiment, the system comprises a deposition tool for receiving a substrate having a layer of insulating material formed thereabove, the layer of insulating material having a plurality of openings formed therein, and performing a deposition process to form a layer of metal at least in the openings in the layer of insulating material, and at least one acoustic generator coupled to the deposition tool to generate sound waves during the deposition process.

Abstract: A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate.

Abstract: Semiconductor devices having fully metal silicided gate electrodes, and methods for making the same, are disclosed. The devices have shallow S/D extensions with depths of less than about 500 Å. The methods for making the subject semiconductor devices employ diffusion of dopant from metal suicides to form shallow S/D extensions, followed by high energy implantation and activation, and metal silicidation to form S/D junctions having metal silicide connect regions and a fully metal silicided electrode.

Abstract: A transistor device is disclosed, having an insulating material disposed between the gate electrode and the drain and source lines, wherein the dielectric constant of the insulating material is 3.5 or less. Accordingly, the capacitance between the gate electrode and the drain and source lines can be reduced, thereby improving signal performance of the field effect transistor with decreased cross talk noise.

Abstract: A novel method of operating repeaters or other hub devices in a local area network, such as one conforming to Ethernet protocol, in which there are a plurality of repeater interfaces of respectively different data rates for communicating with a link partner on a network medium. The methodology comprises determining the data rate of operation of the link partner, and based on that data rate, automatically steering data between the network medium and a selected one of the repeaters. In a preferred embodiment, a network transceiver comprises one or more physical layer devices (PHY), and a plurality of shared data busses corresponding, respectively, to the speeds of operation of the repeaters, for interconnecting the repeaters and one or more of the physical layer devices.

Abstract: With standard DUV lithography technology it is not easy to achieve MOS transistor gates in sub-100 nm range. With the method of trim-etching in HI/O2 plasmas there is an opportunity to use the current lithography tools, to reduce the dimensions of the resist feature, and to achieve sub-100 nm MOS transistor gates for advanced devices. The method of trim-etching in HI/O2 plasmas delivers another factor to control the critical dimension of the MOS devices very accurately. Therefore, this invention helps to significantly reduce the total cost for manufacturing small MOS devices with a critical dimension in the sub-100 nm range.

Abstract: An inspection tool or inspection system can be utilized to determine whether the appropriate pattern is on a reticle. The reticle can be associated with EUV lithographic tools. The system utilizes an at least two wavelengths of light. The light is directed to the reticle at the at least two wavelengths of light.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

Abstract: The present invention is directed to a system and a method for controlling a thin film formation on a moving substrate as part of a process for manufacturing an integrated circuit. The invention involves the use of scatterometry to control the thin film formation process by analyzing the thin film on the moving substrate in a periodic manner. A registration feature associated with the moving substrate can be utilized in conjunction with a signaling system to determine a position of the moving substrate, whereby a repeatable analysis of a corresponding location on the moving substrate can be performed. Scatterometry permits in-situ measurements of thin film formation progress, whereby thin film formation process conditions can be controlled in a feedback loop to obtain a targeted result. Scatterometry can also be facilitated by providing a grating pattern on a non-production portion of the substrate.

Abstract: A method and apparatus for performing manufacturing system analysis upon a manufacturing network. Real-time production data is collected. The real-time production data is stored in a static file database. A real-time data flow is emulated using said real-time production data from said static file database. A reactive function analysis is performed.

Abstract: A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

Abstract: A method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves forming a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of 50 nm or less. The method includes forming a spacer on the sidewalls of a gate, followed by forming source/drain regions by epitaxial growth followed by a deep source/drain implant and anneal. After removal of the spacer, the first angled deep halo implant through the space formed by removal of the spacer and a second annealing at a temperature lower than the first anneal occurs. A second angled halo implant and a third anneal at a temperature less than the second anneal is performed. The microelectronic chip is then silicided and the MOSFET is further completed.