Patents Assigned to Advanced Micro Devices, Incs.
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Publication number: 20250004540Abstract: The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: Advanced Micro Devices, Inc.Inventor: Benjamin Tsien
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Publication number: 20250006290Abstract: Some implementations provide systems methods and devices for integrated circuit self-test. The integrated circuit includes interface circuitry configured to read test data and to write the test data into memory of the integrated circuit. The integrated circuit also includes test circuitry configured to test the interface circuitry based on the test data written into memory of the integrated circuit. Some implementations provide an integrated circuit configured for storing and reading data. The integrated circuit includes circuitry configured to write or read a first portion of data to or from a first memory via BIST circuitry of the first memory until a first BIST counter saturates. The integrated circuit also includes circuitry configured to write or read a second portion of the data to or from a second memory via BIST circuitry of the second memory until a second BIST counter saturates.Type: ApplicationFiled: June 28, 2023Publication date: January 2, 2025Applicant: Advanced Micro Devices, Inc.Inventor: Nehal Patel
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Patent number: 12181955Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 23, 2022Date of Patent: December 31, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Lu Lu, Dong Zhu, Gia Phan, James A. Ott, Nehal Patel, Zang SongGan
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Patent number: 12182412Abstract: An electronic device includes a non-volatile memory and a memory controller. The memory controller selects, from the type-duration table, a duration for which data of a type of data is to be stored in a non-volatile memory. The memory controller writes the data to the non-volatile memory using values of one or more write parameters selected by the memory controller based on the duration. The memory controller sets an expected lifetime value in a record for the data in the expected lifetime table to indicate an expected lifetime of the data in the non-volatile memory.Type: GrantFiled: July 6, 2021Date of Patent: December 31, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Andrew G. Kegel, Steven E. Raasch
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Patent number: 12182611Abstract: An apparatus includes an interrupt cache having cache storage configured to store a plurality of interrupts received from an interrupt source, the plurality of interrupts corresponding to a plurality of interrupt events configured for execution by the plurality of interrupt service routines and a cache manager component configured to generate an interrupt message for transmission to the processing unit, the interrupt message generated to include at least one interrupt of the plurality of interrupts from the cache storage.Type: GrantFiled: December 22, 2022Date of Patent: December 31, 2024Assignees: Advanced Micro Devices, Inc, ATI Technologies ULCInventors: Philip Ng, Anil Kumar
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Patent number: 12181993Abstract: A disclosed method for restoring bus functionality includes detecting, by an automatic bus recovery block, that at least one target device on a bus pulls at least one line of the bus to a low level. The method also includes initiating, by the automatic bus recovery block, a timer to time a duration of the low level of the line. Additionally, the method includes detecting, by the automatic bus recovery block, that the duration of the low level of the line exceeds a predetermined time limit. Furthermore, the method includes alerting, by the automatic bus recovery block, a controller device on the bus that the duration of the low level exceeds the predetermined time limit to reset the line of the bus to a high level. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 9, 2022Date of Patent: December 31, 2024Assignee: Advanced Micro Devices, Inc.Inventors: KaiFei Zhao, LiLi Chen, Wei Han
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Patent number: 12181944Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.Type: GrantFiled: December 27, 2021Date of Patent: December 31, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
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Patent number: 12182396Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.Type: GrantFiled: March 30, 2023Date of Patent: December 31, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
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Patent number: 12181959Abstract: A method and apparatus for predicting and managing a fault in memory includes detecting an error in data. The error is compared to one or more stored errors in a filter, and based upon the comparison, the error is predicted as a transient error or a permanent error for further action.Type: GrantFiled: December 17, 2019Date of Patent: December 31, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas K. Sridharan
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Publication number: 20240427704Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.Type: ApplicationFiled: September 4, 2024Publication date: December 26, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Alexander J. Branover, Benjamin Tsien, Edgar Munoz, Vydhyanathan Kalyanasundharam
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Patent number: 12174747Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.Type: GrantFiled: December 20, 2021Date of Patent: December 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Chintan S. Patel, Guhan Krishnan, Andrew William Lueck, Sreenath Thangarajan
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Patent number: 12175073Abstract: Systems, apparatuses, and methods for reusing remote registers in processing in memory (PIM) are disclosed. A system includes at least a host processor, a memory controller, and a PIM device. When the memory controller receives, from the host processor, an operation targeting the PIM device, the memory controller determines whether an optimization can be applied to the operation. The memory controller converts the operation into N PIM commands if the optimization is not applicable. Otherwise, the memory controller converts the operation into a N?1 PIM commands if the optimization is applicable. For example, if the operation involves reusing a constant value, a copy command can be omitted, resulting in memory bandwidth reduction and power consumption savings. In one scenario, the memory controller includes a constant-value cache, and the memory controller performs a lookup of the constant-value cache to determine if the optimization is applicable for a given operation.Type: GrantFiled: December 31, 2020Date of Patent: December 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Varun Agrawal, Niti Madan
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Patent number: 12172081Abstract: Systems, apparatuses, and methods for detecting personal-space violations in artificial intelligence (AI) based non-player characters (NPCs) are disclosed. An AI engine creates a NPC that accompanies and/or interacts with a player controlled by a user playing a video game. During gameplay, measures of context-dependent personal space around the player and/or one or more NPCs are generated. A control circuit monitors the movements of the NPC during gameplay and determines whether the NPC is adhering to or violating the measures of context-dependent personal space. The control circuit can monitor the movements of multiple NPCs simultaneously during gameplay, keeping a separate score for each NPC. After some amount of time has elapsed, the scores of the NPCs are recorded, and then the scores are provided to a machine learning engine to retrain the AI engines controlling the NPCs.Type: GrantFiled: March 31, 2022Date of Patent: December 24, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Mehdi Saeedi, Ian Charles Colbert, Thomas Daniel Perry, Gabor Sines
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Patent number: 12174742Abstract: A computer processing system having a first memory with a first set of memory pages resident therein and a second memory coupled to the first memory. A resource tracker provides information to instances of a long short-term memory (LSTM) recurrent neural network (RNN). A predictor identifies memory pages from the first set of memory pages for prediction by the one or more LSTM RNN instances. The system groups the memory pages of the identified plurality of memory pages into a number of patterns based on a number of memory accesses per time. An LSTM RNN instance predicts a number of page accesses for each pattern. A second set of memory pages is selected for moving from the first memory to the second memory.Type: GrantFiled: December 14, 2018Date of Patent: December 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Thaleia Dimitra Doudali, Amin Farmahini Farahani
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Patent number: 12174769Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.Type: GrantFiled: March 25, 2022Date of Patent: December 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Gurunath Dollin, Edoardo Prete, Milam Paraschou, Edward Wade Thoenes, Ryan J. Hensley, Gerald R. Talbot
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Patent number: 12176065Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.Type: GrantFiled: June 24, 2022Date of Patent: December 24, 2024Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Xuan Chen, Chih-Hua Hsu, Pradeep Jayaraman, Abdussalam Aburwein
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Patent number: 12175102Abstract: A phase training update circuit operates to perform a phase training update on individual bit lanes. The phase training update circuit adjusts a bit lane transmit phase offset forward a designated number of phase steps, transmits a training pattern, and determines a first number of errors in the transmission. It also adjusts the bit lane transmit phase offset backward the designated number of phase steps, transmits the training pattern, and determines a second number of errors in the transmission. Responsive to a difference between the first number of errors and the second number of errors, the phase training update circuits adjusts a center phase position for the bit lane transmit phase offset of the selected bit lane.Type: GrantFiled: October 11, 2023Date of Patent: December 24, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Scott P. Murphy, Huuhau M. Do
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Patent number: 12174775Abstract: The disclosed computer-implemented method for multi-lane data bus inversion can include receiving data for transmission via a plurality of data lanes, each data lane corresponding to one of a plurality of inversion bits, and, for each data lane within the plurality of data lanes, applying the corresponding inversion bit to each bit within the data lane. Various other methods, apparatuses, and systems are also disclosed.Type: GrantFiled: December 19, 2022Date of Patent: December 24, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Padmini Nujetti, Chao Yu, Michael Tresidder, Daniel McLean
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Publication number: 20240419343Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.Type: ApplicationFiled: August 30, 2024Publication date: December 19, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
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Publication number: 20240419330Abstract: Scheduling processing-in-memory transactions in systems with multiple memory controllers is described. In accordance with the described techniques, an addressing system segments operations of a transaction into multiple microtransactions, where each microtransaction includes a subset of the transaction operations that are scheduled by a corresponding one of the multiple memory controllers. Each transaction, and its associated microtransactions, is assigned a transaction identifier based on a current counter value maintained at the multiple memory controllers, and the multiple memory controllers schedule execution of microtransactions based on associated transaction identifiers to ensure atomic execution of operations for a transaction without interruption by operations of a different transaction.Type: ApplicationFiled: June 19, 2023Publication date: December 19, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alexandru Dutu, Sooraj Puthoor