Patents Assigned to Advanced Micro Devices, Incs.
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Patent number: 12254196Abstract: Systems, apparatuses, and methods for moving data from a memory in a computing system to an I/O device. A system includes a processor, memory, I/O controller, and power management circuitry. An application stores data in the memory that is to be ultimately conveyed to an I/O device. The I/O controller is configured to convey the data to an I/O device according to a service interval. The I/O controller is configured to fetch a first data item from the memory stored by the application, and prefetch one or more additional data items from memory. The first data and prefetched data are stored in a locally accessible buffer of the I/O controller. The I/O controller is then configured to convey each of the first data and one or more data items from the buffer to the I/O device at regular intervals of time during a given period of time, prior to initiating a fetch of additional data from the memory.Type: GrantFiled: November 21, 2022Date of Patent: March 18, 2025Assignee: Advanced Micro Devices, Inc.Inventor: Raul Gutierrez
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Publication number: 20250086515Abstract: Techniques are disclosed for communicating between a machine learning accelerator and one or more processing cores. The techniques include obtaining data at the machine learning accelerator via an input/output die; processing the data at the machine learning accelerator to generate machine learning processing results; and exporting the machine learning processing results via the input/output die, wherein the input/output die is coupled to one or more processor chiplets via one or more processor ports, and wherein the input/output die is coupled to the machine learning accelerator via an accelerator port.Type: ApplicationFiled: November 21, 2024Publication date: March 13, 2025Applicant: Advanced Micro Devices, Inc.Inventor: Maxim V. Kazakov
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Publication number: 20250088193Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.Type: ApplicationFiled: September 13, 2023Publication date: March 13, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Srikanth Reddy Gruddanti, Debasish Dwibedy, Manoj N. Kulkarni, Prasant Kumar Vallur, Priyadarshi Saxena
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Patent number: 12248789Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.Type: GrantFiled: April 28, 2023Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventor: Maxim V. Kazakov
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Patent number: 12248516Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.Type: GrantFiled: February 8, 2024Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Ganesh Dasika, Michael Ignatowski, Michael J Schulte, Gabriel H Loh, Valentina Salapura, Angela Beth Dalton
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Patent number: 12250379Abstract: A method and an apparatus for decoding an image are disclosed. A region of the image is selected and the decoding is selected region and associated metadata is performed. Pixels for a generated for a decoded image based on the decoded selected region and metadata.Type: GrantFiled: November 11, 2022Date of Patent: March 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Andrew S. Pomianowski, Konstantine Iourcha
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Publication number: 20250077320Abstract: A message passing interface processing system is described. In accordance with message passing logic, a node selects an affinity domain for communication of data associated with a message passing interface and selects a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank. The node selects a second rank of a second process of the message passing interface assigned to a second partition of the affinity domain as second partition leader rank, receives the data at the first partition leader rank, and communicates the data from the first partition leader rank to the second partition leader rank.Type: ApplicationFiled: August 30, 2023Publication date: March 6, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Nithya Viswanathan Shyla, Manu Shantharam
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Publication number: 20250077307Abstract: In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the processing element array, the command processor enqueues the fiber in a sleep queue. Further, the command processor enqueues the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array. Based on the fiber being in the check queue, the command processor enqueues a dependent fiber in the ready queue that depends from the fiber.Type: ApplicationFiled: August 31, 2023Publication date: March 6, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Ali Arda Eker, Martha Massee Barker, Anthony Thomas Gutierrez
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Publication number: 20250077379Abstract: Techniques for performing memory operations are disclosed herein. The techniques include obtaining statistics for operation of a device, the statistics including either or both of performance statistics and memory access statistics; generating a plurality of visualizations of the statistics in one of an overlay mode or a scene annotation mode; and displaying the plurality of visualizations.Type: ApplicationFiled: September 4, 2023Publication date: March 6, 2025Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guennadi Riguer, Christopher J. Brennan
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Patent number: 12242893Abstract: A system and method for ranking computing resources in a distributed computing marketplace is disclosed. Ranking may be based on the performance factors that the system predicts will have the greatest impact on the particular application the user plans to run. A performance database stores historical performance data for applications that have been executed on multiple different computer systems. The database is checked to see if the application, or one similar, has already been run on any of the computing systems participating in the distributed computing marketplace. If so, the existing performance data is used to predict which performance factors will have the greatest impact on the application. Those factors are then used to rank the available computing systems options for the user.Type: GrantFiled: August 18, 2021Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Max Alt, Gabriel Martin
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Patent number: 12243578Abstract: A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.Type: GrantFiled: December 20, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Aaron John Nygren, Karthik Gopalakrishnan, Tsun Ho Liu
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Patent number: 12242407Abstract: An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: November 8, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Samuel Abraham Lipson, Eric Christopher Morton, Bryan P. Broussard, Vydhyanathan Kalyanasundharam
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Patent number: 12242384Abstract: Methods, devices, and systems for prefetching data. First data is loaded from a first memory location. The first data in cached in a cache memory. Other data is prefetched to the cache memory based on a compression of the first data and a compression of the other data. In some implementations, the compression of the first data and the compression of the other data are determined based on metadata associated with the first data and metadata associated with the other data. In some implementations, the other data is prefetched to the cache memory based on a total of a compressed size of the first data and a compressed size of the other data being less than a threshold size. In some implementations, the other data is not prefetched to the cache memory based on the other data being uncompressed.Type: GrantFiled: January 27, 2023Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Pazhani Pillai, Harish Kumar Kovalam Rajendran
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Patent number: 12242828Abstract: A compilation technique is provided. The technique includes including a first instruction into a first executable for a first auxiliary processor, wherein the first instruction specifies execution by the first auxiliary processor; and including a second instruction into the first executable, wherein the second instruction targets resources that have affinity with the first auxiliary processor.Type: GrantFiled: November 1, 2022Date of Patent: March 4, 2025Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Mingliang Lin
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Patent number: 12242325Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.Type: GrantFiled: March 30, 2022Date of Patent: March 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: William Robert Alverson, Amitabh Mehra, Jerry Anton Ahrens, Grant Evan Ley, Anil Harwani, Joshua Taylor Knight
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Patent number: 12236529Abstract: Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.Type: GrantFiled: December 27, 2021Date of Patent: February 25, 2025Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Christopher J. Brennan, Randy Wayne Ramsey, Nishank Pathak, Ricky Wai Yeung Iu, Jimshed Mirza, Anthony Chan
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Patent number: 12235756Abstract: Near-memory compute elements perform memory operations and temporarily store at least a portion of address information for the memory operations in local storage. A broadcast memory command is then issued to the near-memory compute elements that causes the near-memory compute elements to perform a subsequent memory operation using their respective address information stored in the local storage. This allows a single broadcast memory command to be used to perform memory operations across multiple memory elements, such as DRAM banks, using bank-specific address information. In one implementation, the approach is used to process workloads with irregular updates to memory while consuming less command bus bandwidth than conventional approaches. Implementations include using conditional flags to selectively designate address information in local storage that is to be processed with the broadcast memory command.Type: GrantFiled: December 21, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Shaizeen Aga, Johnathan Alsop, Nuwan Jayasena
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Patent number: 12237026Abstract: The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: November 7, 2022Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Vaibhav Anand Srivastava, Pankaj Kumar
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Patent number: 12236555Abstract: A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color component and the third color component based on the directional color difference weightings, interpolate a color value of the pixel from the one color component and the color differences and provide a color image for display.Type: GrantFiled: December 23, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Linwei Yu, Jiangli Ye, Yang Ling, Hui Zhou
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Patent number: 12236109Abstract: A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap parameter corresponds to a re-usability index for the functions. The fabric manager circuitry allocate a first programmable integrated circuit (IC) device to perform a first function of the input application based on the task graph, the data graph, and the function popularity heap parameter.Type: GrantFiled: May 24, 2023Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Pratik Mishra, Sergey Blagodurov, Atul Kumar Sujayendra Sandur
