Patents Assigned to Advanced Micro Devices, Incs.
  • Patent number: 12205193
    Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi
  • Patent number: 12204466
    Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes executing at least one application in the dockable device using a first processor, and initiating an application migration for the at least one application from the first processor to a second processor in a docking station responsive to determining that the dockable device is in a docked state, wherein the at least one application continues to execute during the application migration from the first processor to the second processor.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan Lawrence Campbell, Yuping Shen
  • Patent number: 12204908
    Abstract: A branch predictor predicts a first outcome of a first branch in a first block of instructions. Fetch logic fetches instructions for speculative execution along a first path indicated by the first outcome. Information representing a remainder of the first block is stored in response to the first predicted outcome being taken. In response to the first branch instruction being not taken, the branch predictor is restarted based on the remainder block. In some cases, entries corresponding to second blocks along speculative paths from the first block are accessed using an address of the first block as an index into a branch prediction structure. Outcomes of branch instructions in the second blocks are concurrently predicted using a corresponding set of instances of branch conditional logic and the predicted outcomes are used in combination with the remainder block to restart the branch predictor in response to mispredictions.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marius Evers, Douglas Williams, Ashok T. Venkatachar, Sudherssen Kalaiselvan
  • Patent number: 12204911
    Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew T. Sobel, Joshua James Lindner, Neil N. Marketkar, Kai Troester, Emil Talpes, Ashok Tirupathy Venkatachar
  • Patent number: 12205897
    Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 12204754
    Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, James Raymond Magro
  • Patent number: 12204459
    Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Donald W. McCauley, William E. Jones
  • Patent number: 12204900
    Abstract: Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nuwan S Jayasena
  • Patent number: 12205884
    Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of maintaining a similar capacitance for design reuse across multiple semiconductor fabrication processes are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. Subsequent semiconductor fabrication processes typically increase a number of metal plates that can be formed in the dielectric layer, such as an oxide layer, between two signal nets. To permit design reuse across multiple semiconductor fabrication processes, for a particular MIM capacitor designated to maintain a same capacitance, the additional metal plates for the particular MIM capacitor are formed as floating nets.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Regina Tien Schmidt
  • Patent number: 12205218
    Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Leather, Michael Mantor
  • Patent number: 12204454
    Abstract: Systems, apparatuses, and methods for employing system probe filter aware last level cache insertion bypassing policies are disclosed. A system includes a plurality of processing nodes, a probe filter, and a shared cache. The probe filter monitors a rate of recall probes that are generated, and if the rate is greater than a first threshold, then the system initiates a cache partitioning and monitoring phase for the shared cache. Accordingly, the cache is partitioned into two portions. If the hit rate of a first portion is greater than a second threshold, then a second portion will have a non-bypass insertion policy since the cache is relatively useful in this scenario. However, if the hit rate of the first portion is less than or equal to the second threshold, then the second portion will have a bypass insertion policy since the cache is less useful in this case.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul James Moyer, Jay Fleischman
  • Patent number: 12197533
    Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Pramod Vasant Argade, Swapnil P. Sakharshete, Maxim V. Kazakov, Alexander M. Potapov
  • Patent number: 12197329
    Abstract: Systems and methods of cache flushing include receiving, from a software application, a first cache flush request to perform a range-based cache flush of a contiguous virtual address range within a virtual memory that maps to a physical memory. A single cache walk is triggered via a second cache flush request to a cache. The single cache walk performs the range-based cache flush for the contiguous physical address range from a beginning address of the contiguous physical address range to an ending address of the contiguous physical address range in response to the first cache flush request.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael W. Boyer, Preyesh Dalmia
  • Patent number: 12198271
    Abstract: Devices and methods for multi-resolution geometric representation for ray tracing are described which include casting a ray in a space comprising objects represented by geometric shapes and approximating a volume of the geometric shapes using an accelerated hierarchy structure. The accelerated hierarchy structure comprises first nodes each representing a volume of one of the geometric shapes in the space and second nodes each representing an approximate volume of a group of the geometric shapes. When the ray is determined to intersect a bounding box of a second node representing one group of the geometric shapes, a selection is made between traversal and non-traversal of other second nodes based on a LOD for representing the volume of the one group of geometric shapes.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 14, 2025
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Sho Ikeda, Paritosh Vijay Kulkarni, Takahiro Harada
  • Patent number: 12198295
    Abstract: A technique for performing convolution operations is disclosed. The technique includes performing a first convolution operation based on a first convolutional layer input image to generate at least a portion of a first convolutional layer output image; while performing the first convolution operation, performing a second convolution operation based on a second convolutional layer input image to generate at least a portion of a second convolutional layer output image, wherein the second convolutional layer input image is based on the first convolutional layer output image; storing the portion of the first convolutional layer output image in a first memory dedicated to storing image data for convolution operations; and storing the portion of the second convolutional layer output image in a second memory dedicated to storing image data for convolution operations.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Y. Chow, Vidyashankar Viswanathan, Richard E. George
  • Patent number: 12197735
    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 14, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
  • Patent number: 12189530
    Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.
    Type: Grant
    Filed: March 29, 2024
    Date of Patent: January 7, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Moyer
  • Patent number: 12189535
    Abstract: The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: January 7, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Ganesh Balakrishnan, Kevin M. Lepak, Amit P. Apte
  • Patent number: 12190174
    Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: January 7, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexandru Dutu, Sergey Blagodurov, Anthony T. Gutierrez, Matthew D. Sinclair, David A. Wood, Bradford M. Beckmann
  • Patent number: 12190225
    Abstract: A technique for manipulating a generic tensor is provided. The technique includes receiving a first request to perform a first operation on a generic tensor descriptor associated with the generic tensor, responsive to the first request, performing the first operation on the generic tensor descriptor, receiving a second request to perform a second operation on generic tensor raw data associated with the generic tensor, and responsive to the second request, performing the second operation on the generic tensor raw data.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: January 7, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chao Liu, Daniel Isamu Lowell, Wen Heng Chung, Jing Zhang