Patents Assigned to Advanced Micro Devices, Incs.
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Patent number: 12236134Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.Type: GrantFiled: September 27, 2022Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Mahzabeen Islam, Shaizeen Dilawarhusen Aga, Johnathan Robert Alsop, Mohamed Assem Abd ElMohsen Ibrahim, Nuwan S Jayasena
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Patent number: 12235708Abstract: Devices and methods for cache prefetching are provided. A device is provided which comprises a quality of service (QOS) component having first assigned registers used to store data to execute a program, a plurality of non-QOS components having second assigned registers used to store data to execute the program and a power management controller, in communication with the QOS component and the non-QOS components. The power management controller is configured to issue fences for the non-QOS components when it is determined that one or more of the non-QOS components are idle, issue a fence for the QOS component when the fences for the non-QOS components are completed and enter a reduced power state when the fences for the non-QOS components and the fence for the QOS component are completed.Type: GrantFiled: September 23, 2021Date of Patent: February 25, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry, Mihir Shaileshbhai Doctor
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Publication number: 20250061071Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.Type: ApplicationFiled: October 8, 2024Publication date: February 20, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Hideki Kanayama, YuBin Yao
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Patent number: 12229563Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: June 30, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Sree Harsha Kosuru, Eric Dixon, Erik Swanson, Michael Estlick, Patrick Michael Lowry
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Patent number: 12231120Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: June 30, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Jagadeesh Anathahalli Singrigowda, Girish A S, Aniket Bharat Waghide, Prasant Kumar Vallur
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Patent number: 12229570Abstract: Block data load with transpose techniques are described. In one example, an input is received, at a control unit, specifying an instruction to load a block of data to at least one memory module using a transpose operation. Responsive to the receiving the input by the control unit, the block of data is caused to be loaded to the at least one memory module by transposing the block of data to form a transposed block of data and storing the transposed block of data in the at least one memory.Type: GrantFiled: September 25, 2022Date of Patent: February 18, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Bin He, Michael John Mantor, Brian Emberling, Liang Huang, Chao Liu
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Patent number: 12225299Abstract: A system for automatic image band detection includes concurrently capturing a first image of a scene with a first camera having a first exposure time and a second image of the scene with a second camera having a second exposure time. The system detects image banding for one of the first camera and the second camera based on the first image and the second image.Type: GrantFiled: December 28, 2021Date of Patent: February 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Po-Min Wang, MuFan Yen
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Patent number: 12222797Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: December 19, 2022Date of Patent: February 11, 2025Assignee: Advanced Micro Devices, Inc.Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
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Publication number: 20250044966Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: July 31, 2023Publication date: February 6, 2025Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Nicholas Carmine DeFiore, Sridhar Varadharajulu Gada, James R. Magro, Michael L. Choate, Wayne Paul Rodrigue, NrusimhaVamsi Krishna Godavarti, Robert Gentile, Roozbeh Paribakht, Anwar Kashem
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Patent number: 12217059Abstract: The disclosed device a controller that sets an iteration counter for a loop based on an iteration value read from a loop iteration instruction for the loop. The controller also updates the iteration counter based on a number of times a loop heading instruction for the loop is decoded. When the iteration counter reaches an end value, the controller selects a not taken identifier for the loop to be fetched, to avoid a branch misprediction. Various other methods, systems, and computer-readable media are also disclosed.Type: GrantFiled: March 30, 2023Date of Patent: February 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Toufic Freij, Gabriel H. Loh, Onur Kayiran
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Patent number: 12217021Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.Type: GrantFiled: July 7, 2023Date of Patent: February 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Bin He, Shubh Shah, Michael Mantor
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Patent number: 12216590Abstract: A cache controller of a processing system implementing a non-uniform memory architecture (NUMA) adjusts a cache replacement priority of local and non-local data stored at a cache based on a cache replacement policy. Local data is data that is accessed by the cache via a local memory channel and non-local data is data that is accessed by the cache via a non-local memory channel. The cache controller assigns priorities to local and non-local data stored at the cache based on a cache replacement policy and selects data for replacement at the cache based, at least in part, on the assigned priorities.Type: GrantFiled: June 9, 2023Date of Patent: February 4, 2025Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Saurabh Sharma, Hashem Hashemi, Guennadi Riguer
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Patent number: 12217061Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.Type: GrantFiled: April 28, 2023Date of Patent: February 4, 2025Assignee: Advanced Micro Devices, Inc.Inventor: Maxim V. Kazakov
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Patent number: 12216539Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).Type: GrantFiled: October 31, 2022Date of Patent: February 4, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas Sridharan, Majed Valad Beigi
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Publication number: 20250036467Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.Type: ApplicationFiled: June 17, 2024Publication date: January 30, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Sonu Arora, Daniel L. Bouvier
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Publication number: 20250037750Abstract: The disclosed systems and methods include a control circuit for entering a low power state of a memory by preserving a context of the memory's controller and power gating the memory's physical layer. The context can be saved to a non-volatile memory device or by keeping a retention supply voltage to a register of the memory controller. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: July 25, 2024Publication date: January 30, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Indrani Paul, Benjamin Tsien, James R. Magro
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Patent number: 12210780Abstract: In accordance with described techniques for filtered responses to memory operation messages, a computing system or computing device includes a memory system that receives messages. A filter component in the memory system receives the responses to the memory operation messages, and filters one or more of the responses based on a filterable condition. A tracking logic component tracks the one or more responses as filtered responses for communication completion.Type: GrantFiled: September 28, 2022Date of Patent: January 28, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Johnathan Robert Alsop, Shaizeen Dilawarhusen Aga, Mohamed Assem Abd Elmohsen Ibrahim
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Patent number: 12212322Abstract: A clock driver with duty cycle correction includes a first driver circuit, a second driver circuit, and a correction logic circuit. The first driver circuit performs duty cycle correction on a clock input signal and has parameters selected for a first frequency range of the clock input signal. The second driver circuit is nested with the first driver circuit and performs duty cycle correction on the clock input signal with parameters selected for a second frequency range of the clock input signal lower than the first frequency range. The correction logic circuit provides correction signals to a selected one of the first driver circuit and the second driver circuit. The clock driver provides a duty cycle corrected clock signal from the selected one of the first driver circuit and the second driver circuit based on a selected frequency range of the clock input signal.Type: GrantFiled: May 11, 2023Date of Patent: January 28, 2025Assignee: Advanced Micro Devices, Inc.Inventors: Raghavendra Rukmani Gowrishankar, Milind Gopal Agrawal
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Patent number: 12212337Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.Type: GrantFiled: March 30, 2023Date of Patent: January 28, 2025Assignees: XILINX, INC., Advanced Micro Devices, Inc.Inventors: Kumar Rahul, John J. Wuu, Santosh Yachareni
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Publication number: 20250028010Abstract: A computer-implemented method for abnormal power connection detection can include receiving, by at least one processor, a power signal by a power connector and an additional power signal by an additional power connector. The method can additionally include performing, by the at least one processor, one or more measurements of the additional power signal. The method can also include carrying out, by the at least one processor, one or more response procedures based on the one or more measurements. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: July 19, 2023Publication date: January 23, 2025Applicant: Advanced Micro Devices, Inc.Inventors: ChaiLin Yu, YanHe Qi, JiJun Shi
