Abstract: Embodiments include methods, systems, and articles of manufacture directed to identifying transient data upon storing the transient data in a cache memory, and invalidating the identified transient data in the cache memory.

Abstract: A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

Abstract: Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying.

Abstract: Methods, systems, and computer program products are provided for hardware enforced data protection mechanisms to protect software data structures. Software data structures can be protected against malicious software or software code errors that may result in data/buffer overruns or failures in computing systems. Software data structures are identified that need to be validated before they are used by software programs. A hardware mechanism receives instructions from various security privilege levels and validates an entire software data structure before the software data structure is used by software programs. Being able to detect whether a software data structure is corrupted improves defenses and security against malicious or erroneous code, provides a method for early identification, isolation, ease of debugging of software, and protects overall system integrity in computer systems and applications thereof.

Abstract: A processor, a method and a computer-readable storage medium for tracking a return address are provided. The processor comprises a hardware register and logic configured to receive a call instruction. The logic is further configured to, based on the call instruction, encrypt a return address, store the encrypted return address onto a first address in a stack and store the first address on the hardware register.

Abstract: A data processor includes an execution unit having a multiple number of redundant resources, and a configuration circuit having first and second modes, wherein in the first mode, the configuration circuit enables the multiple number of redundant resources, and in the second mode, the configuration circuit disables the multiple number of redundant resources.

Abstract: A processor, a method and a computer-readable storage medium for encrypting a return address are provided. The processor comprises hardware logic configured to encrypt an instruction pointer and push the encrypted instruction pointer onto a stack. The logic is further configured to retrieve the encrypted instruction pointer from the stack, decrypt the instruction pointer and redirect execution to the decrypted instruction pointer.

Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.

Abstract: A method of fabricating a semiconductor device having a transistor with a metal gate electrode and a gate dielectric layer includes forming a protective layer on the gate dielectric layer and forming a metal gate electrode over the protective layer. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract: A processor power limiter and method is provided. The processor includes a first programmable location configured to store a processor power target. A power monitor is configured to estimate a power dissipation due to processor load. A power controller is configured to adjust a processor power parameter based on the power target and the power dissipation. The processor may include an interface for an operating system. A second programmable location may be configured to store a software processor power target accessible by the operating system. The processor may also include a sideband interface for an external agent. A third programmable location may be configured to store an agent processor power target accessible by the external agent. The power controller may be configured to adjust a processor core voltage and/or frequency such that the power dissipation stays below the processor power target, software processor power target and the agent processor power target.

Abstract: A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.

Abstract: A processor discards spill data from a memory hierarchy in response to the final access to the spill data has been performed by a compiled program executing at the processor. In some embodiments, the final access determined based on a special-purpose load instruction configured for this purpose. In some embodiments the determination is made based on the location of a stack pointer indicating that a method of the executing program has returned, so that data of the returned method that remains in the stack frame is no longer to be accessed. Because the spill data is discarded after the final access, it is not transferred through the memory hierarchy.

Abstract: The present invention provides a method and apparatus for use with a hierarchical cache system. The method may include concurrently flushing one or more first caches and a second cache of a multi-level cache. Each first cache is smaller and at a lower level in the multi-level cache than the second level cache.

Abstract: A device instructs a power supply to provide a current to a power cycling test structure that includes a heat source interconnected with a package, via a first level interconnect mechanism, and a printed circuit board (PCB) interconnected with the package, via a second level interconnect mechanism. The device also monitors thermal feedback associated with the heat source, and monitors, based on the provided current, voltage feedback associated with the power cycling test structure. The device further determines a thermal profile of the power cycling test structure based on the thermal feedback and the voltage feedback.

Abstract: A system, a computer program product, and a computer-implemented method are provided for automatically generating a LVS rule file, and/or for automatically generating a regression test data suite.

Abstract: Provided herein is a method for optimizing communication for system calls. The method includes storing a system call for each work item in a wavefront and transmitting said stored system calls to a processor for execution. The method also includes receiving a result to each work item in the wavefront responsive to said transmitting.

Abstract: A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.

Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

Abstract: A method for establishing connectivity for a mobile device including a plurality of communication interfaces is provided. A power state of the mobile device is monitored. A first one of the communication interfaces is selected based on the power state. Connectivity is established to a remote network using the first communication interface.

Abstract: The described embodiments include a cache with a plurality of banks that includes a cache controller. In these embodiments, the cache controller determines a value representing non-native cache blocks stored in at least one bank in the cache, wherein a cache block is non-native to a bank when a home for the cache block is in a predetermined location relative to the bank. Then, based on the value representing non-native cache blocks stored in the at least one bank, the cache controller determines at least one bank in the cache to be transitioned from a first power mode to a second power mode. Next, the cache controller transitions the determined at least one bank in the cache from the first power mode to the second power mode.