Abstract: Methods, systems, and computer readable storage media embodiments allow for low overhead context switching of threads. In embodiments, applications, such as, but not limited to, iterative data-parallel applications, substantially reduce the overhead of context switching by adding a user or higher-level program configurability of a state to be saved upon preempting of a executing thread. These methods, systems, and computer readable storage media include aspects of running a group of threads on a processor, saving state information by respective threads in the group in response to a signal from a scheduler, and pre-empting running of the group after the saving of the state information.

Abstract: A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.

Abstract: A method for executing processes within a computer system is provided. The method includes determining when to switch from a first process, executing within the computer system, to executing another process. Execution of the first process corresponds to a computer system storage location. The method also includes switching to executing the other process based upon a time quantum and resuming execution of the first process after the time quantum has lapsed, the resuming corresponding to the storage location.

Abstract: A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.

Abstract: In response to a processor receiving data associated with a shared memory location, a contention blocking buffer stores a memory address of the shared memory location. In response to a probe seeking to take ownership of the shared memory location, the contention blocking buffer determines if the memory address indicated by the probe is stored at the contention blocking buffer. If so, the contention blocking buffer blocks the probe, thereby preventing another processor from taking ownership of the shared memory location.

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract: Embodiments include methods, systems and computer readable media configured to execute a first kernel (e.g. compute or graphics kernel) with reduced intermediate state storage resource requirements. These include executing a first and second (e.g. prefetch) kernel on a data-parallel processor, such that the second kernel begins executing before the first kernel. The second kernel performs memory operations that are based upon at least a subset of memory operations in the first kernel.

Abstract: The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions.

Abstract: Methods and apparatus are provided for implementing the advanced encryption standard. The apparatus comprises a first multiplexer receiving during a first cycle a data word, a substitution transformation of the data word and inverse substitution transformation of the data word to provide a first output. During the next cycle, a second multiplexer receives the first output, a mixed column transformation of the first output and an inverse mixed column transformation of the first output to provide a second output. Also in the next cycle, the second output is added to a round key to provide one round of an encoded or decoded digital word compliant with the advanced encryption standard with cycle-by-cycle throughput. The method comprises shifting a received data word and processing the shifted data word using a substitution transformation (encoding) or an inverse substitution transformation (decoding) during a first cycle in an advanced encryption standard unit of a processor.

Abstract: A method for managing work distribution in a processor including a plurality of instruction data modules, is provided. The method includes analyzing work units received by the processor and comparing the utilization level in each active module within the plurality with a first predetermined threshold. The work units are distributed across selected ones of the modules within the plurality based upon the analyzing and the comparing.

Abstract: Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Abstract: Improved memory management in a processor is provided using garbage collection utilities. The processor includes higher performance memory units and lower performance memory units and a memory management unit. The memory management unit includes a garbage collection utility programmed to identify high use memory blocks and low use memory blocks within the higher and lower performance memory units. The memory management unit is also configured to move the high use memory blocks to higher performance memory and move the low use memory blocks to lower performance memory. The method comprises determining performance characteristics of available memory to identify higher performance memory and lower performance memory. Next memory block use metrics are analyzed to identify high use memory blocks and low use memory blocks. Finally, high use memory blocks are moved to the higher performance memory while the low use memory blocks are moved to the lower performance memory.

Abstract: A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory.

Abstract: An apparatus and method is disclosed for a computer processor configured to access a memory shared by a plurality of processing cores and to execute a plurality of memory access operations in a transactional mode as a single atomic transaction and to suspend the transactional mode in response to determining an implicit suspend condition, such as a program control transfer. As part of executing the transaction, the processor marks data accessed by the speculative memory access operations as being speculative data. In response to determining a suspend condition (including by detecting a control transfer in an executing thread) the processor suspends the transactional mode of execution, which includes setting a suspend flag and suspending marking speculative data. If the processor later detects a resumption condition (e.g., a return control transfer corresponding to a return from the control transfer), the processor is configured to resume the marking of speculative data.

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

Abstract: A method of partitioning a data cache comprising a plurality of sets, the plurality of sets comprising a plurality of ways, is provided. Responsive to a stack data request, the method stores a cache line associated with the stack data in one of a plurality of designated ways of the data cache, wherein the plurality of designated ways is configured to store all requested stack data.

Abstract: The described embodiments include a core that uses predictions for store-to-load forwarding. In the described embodiments, the core comprises a load-store unit, a store buffer, and a prediction mechanism. During operation, the prediction mechanism generates a prediction that a load will be satisfied using data forwarded from the store buffer because the load loads data from a memory location in a stack. Based on the prediction, the load-store unit first sends a request for the data to the store buffer in an attempt to satisfy the load using data forwarded from the store buffer. If data is returned from the store buffer, the load is satisfied using the data. However, if the attempt to satisfy the load using data forwarded from the store buffer is unsuccessful, the load-store unit then separately sends a request for the data to a cache to satisfy the load.

Abstract: Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments are directed to a transcoding system that shares the workload of video transcoding through the use of multiple central processing unit (CPU) cores and/or one or more graphical processing units (GPU), including the use of two components within the GPU: a dedicated hardcoded or programmable video decoder for the decode step and compute shaders for scaling and encoding. The system combines usage of an industry standard Microsoft DXVA method for using the GPU to accelerate video decode with a GPU encoding scheme, along with an intermediate step of scaling the video.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: A method and apparatus for accelerated shared data migration between cores. Using an Always Migrate protocol, when a migratory probe hits a directory entry in either modified or owned state, the entry is transitioned to an owned state, and a source done command is sent without sending cache block ownership or state information to the directory.