Patents Assigned to Advanced Micro Devics, Inc.
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Patent number: 11703930Abstract: Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.Type: GrantFiled: July 21, 2021Date of Patent: July 18, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Indrani Paul, Sriram Sambamurthy, Larry David Hewitt, Kevin M. Lepak, Samuel D. Naffziger, Adam Neil Calder Clark, Aaron Joseph Grenat, Steven Frederick Liepe, Sandhya Shyamasundar, Wonje Choi, Dana Glenn Lewis, Leonardo de Paula Rosa Piga
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Patent number: 11704277Abstract: Systems and methods for efficiently routing qubits in a quantum computing system include selecting bubble nodes and routing qubits to the bubble nodes. The systems and methods further include dividing a system of nodes into regions and selecting a bubble node for each region. The systems and methods further include using super bubble nodes with reliable links connected to other super bubble nodes and bubble nodes to improve cross-region operations.Type: GrantFiled: December 16, 2019Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Majed Valad Beigi, Yasuko Eckert, Dongping Zhang
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Patent number: 11704183Abstract: A data processor includes provides memory commands to a memory channel according to predetermined criteria. The data processor includes a first error code generation circuit, a second error code generation circuit, and a queue. The first error code generation circuit generates a first type of error code in response to data of a write request. The second error code generation circuit generates a second type of error code for the write request, the second type of error code different from the first type of error code. The queue is coupled to the first error code generation circuit and to the second error code generation circuit, for provides write commands to an interface, the write commands including the data, the first type of error code, and the second type of error code.Type: GrantFiled: December 7, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Kedarnath Balakrishnan, James R. Magro, Kevin Michael Lepak, Vilas Sridharan
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Patent number: 11703937Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.Type: GrantFiled: September 23, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Patent number: 11703932Abstract: A data fabric routes requests between the plurality of requestors. A probe filter tracks the state of cached lines of memory at a probe filter coupled to the data fabric. Responsive to the data fabric leaving a non-operational power state while all requestors that are probe filter clients are in a non-operational power state, the power management controller delays a probe filter initialization state in which data regarding cached lines is initialized following the non-operational power state.Type: GrantFiled: June 24, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Amit P. Apte
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Publication number: 20230214232Abstract: A processing device is provided which comprises memory and a processor, in communication with the memory. The processor is configured to acquire information indicating a sensory perception of a user, determine settings for one or more parameters used to control operation of the device based on the information indicating the sensory perception of the user and control the operation of the device by tuning the one or more parameters according to the determined settings.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Micro Devices, Inc.Inventor: William Herz
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Publication number: 20230214345Abstract: A device in an interconnect network is provided. The device comprises an end point processor comprising end point memory and an interconnect network link in communication with an interconnect network switch. The device is configured to issue, by the end point processor, a request to send data from the end point memory to other end point memory of another end point processor of another device in the interconnect network and provide, to the interconnect network switch, the request using memory addresses from a global memory address map which comprises a first global memory address range for the end point processor and a second global memory address range for the other end point processor.Type: ApplicationFiled: December 30, 2021Publication date: July 6, 2023Applicant: Advanced Micro Devices, Inc.Inventor: Brock A. Taylor
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Patent number: 11693778Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.Type: GrantFiled: December 11, 2020Date of Patent: July 4, 2023Assignee: Advanced Micro Devices, Inc.Inventor: John Kelley
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Patent number: 11693813Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: GrantFiled: May 30, 2019Date of Patent: July 4, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
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Patent number: 11694739Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.Type: GrantFiled: December 29, 2021Date of Patent: July 4, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
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Patent number: 11694081Abstract: Systems, methods, and devices for pruning a convolutional neural network (CNN). A subset of layers of the CNN is chosen, and for each layer of the subset of layers, how salient each filter in the layer is to an output of the CNN is determined, a subset of the filters in the layer is determined based on the salience of each filter in the layer, and the subset of filters in the layer is pruned. In some implementations, the layers of the subset of layers of the CNN are non-contiguous. In some implementations, the subset of layers includes odd numbered layers of the CNN and excludes even numbered layers of the CNN. In some implementations, the subset of layers includes even numbered layers of the CNN and excludes odd numbered layers of the CNN.Type: GrantFiled: June 28, 2019Date of Patent: July 4, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Arun Coimbatore Ramachandran, Chandra Kumar Ramasamy, Prakash Sathyanath Raghavendra, Keerthan Subraya Shagrithaya
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Patent number: 11694367Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.Type: GrantFiled: April 8, 2022Date of Patent: July 4, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Saurabh Sharma, Laurent Lefebvre, Sagar Shankar Bhandare, Ruijin Wu
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Publication number: 20230206379Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander Fuad Ashkar, Mangesh P. Nijasure, Rakan Z. Khraisha, Manu Rastogi
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Publication number: 20230207038Abstract: Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Anwar Kashem, Craig Daniel Eaton, Pouya Najafi Ashtiani
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Publication number: 20230206540Abstract: A technique for performing ray tracing operations is provided. The technique includes combining one or more common exponent values of a compressed box node with one or more minimum vertex mantissas of the compressed box node and one or more maximum vertex mantissas of the compressed box node to obtain one or more minimum vertices and one or more maximum vertices; and combining a minimum vertex of the one or more minimum vertices and a maximum vertex of the one or more maximum vertices to obtain a bounding box for a compressed box data item of the compressed box node.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Chen Huang
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Publication number: 20230206541Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing through a bounding volume hierarchy to an instance node; performing an instance node transform using common circuitry; traversing to a leaf node of the bounding volume hierarchy; and performing an intersection test for the leaf node using the common circuitry.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Fataneh F. Ghodrat, Jeffrey Christopher Allan
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Publication number: 20230205539Abstract: Devices, methods and systems for managing resources in a computing device. Information regarding resource usage is captured. A prediction is generated, based on the information, that resource usage by a processor will exceed a threshold during an upcoming time. An operating parameter of the processor is adjusted, based on the prediction. In some implementations, information regarding memory bandwidth is captured. A prediction is generated, based on the information, that a memory region stored in a first memory device will be addressed by a memory intensive instruction during an upcoming time period. Data stored in the memory region is moved to a second memory device, based on the prediction.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Masab Ahmad
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Publication number: 20230206539Abstract: Methods and systems are disclosed for traversing nodes in a BVH tree by an intersection engine. Techniques disclosed comprise receiving, by the intersection engine, a traversal instruction, including a tracing-mode, ray data, and an identifier of a node to be traversed. Where the tracing-mode includes a closest hit mode and a first hit mode. If the node to be traversed is an internal node, the intersection engine determines, based on the tracing-mode, an order in which children nodes of the node are to be next traversed and output identifiers of the children nodes in the determined order.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: John Alexandre Tsakok, Skyler Jonathon Saleh
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Publication number: 20230206368Abstract: A technique for operating a processing device is disclosed. The method includes configuring at least one switch to interconnect one or more selected IP to the processing device, receiving an activation signal associated with the at least one switch based on the one or more selected IP, in response to the activation signal, causing the at least one switch to disable connection to the one or more selected IP, and verifying access to the one or more selected IP is disabled.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
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Publication number: 20230205297Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.Type: ApplicationFiled: December 27, 2021Publication date: June 29, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Thomas J. Gibney, Stephen V. Kosonocky, Mihir Shaileshbhai Doctor, John P. Petry, Indrani Paul, Benjamin Tsien, Christopher T. Weaver
