Patents Assigned to Advanced Micro Devics, Inc.
  • Dynamic random-access memory (DRAM) training acceleration
    Patent number: 11742043
    Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: YuBin Yao, Eric M. Scott, TieFeng Liu
  • Memory pools in a memory model for a unified computing system
    Patent number: 11741019
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Method and apparatus for managing processor functionality
    Patent number: 11740944
    Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: August 29, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Amitabh Mehra, Anil Harwani, William Robert Alverson, Jerry Anton Ahrens, Jr., Charles Sum Yuen Lee, John William Abshier
  • Overlapping visibility and render passes for same frame
    Patent number: 11741653
    Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya, Kiia Kallio
  • Artificial neural network emulation of hotspots
    Patent number: 11741397
    Abstract: Methods, devices, and systems for emulating a compute kernel with an ANN. The compute kernel is executed on a processor, and it is determined whether the compute kernel is a hotspot kernel. If the compute kernel is a hotspot kernel, the compute kernel is emulated with an ANN, and the ANN is substituted for the compute kernel.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nicholas Malaya
  • WAVEFRONT SELECTION AND EXECUTION
    Publication number: 20230266975
    Abstract: Techniques are provided for executing wavefronts. The techniques include at a first time for issuing instructions for execution, performing first identifying, including identifying that sufficient processing resources exist to execute a first set of instructions together within a processing lane; in response to the first identifying, executing the first set of instructions together; at a second time for issuing instructions for execution, performing second identifying, including identifying that no instructions are available for which sufficient processing resources exist for execution together within the processing lane; and in response to the second identifying, executing an instruction independently of any other instruction.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Maxim V. Kazakov
  • Semi-sorting compression with encoding and decoding tables
    Patent number: 11736119
    Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander D. Breslow, Nuwan Jayasena, John Kalamatianos
  • Programmable error correction code encoding and decoding logic
    Patent number: 11734114
    Abstract: A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Ross V. La Fetra
  • Precise shadowing and adjustment of on-die timers in low power states
    Patent number: 11734151
    Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Pravesh Gupta
  • Hardware assisted fine-grained data movement
    Patent number: 11734059
    Abstract: A processor includes a task scheduling unit and a compute unit coupled to the task scheduling unit. The task scheduling unit performs a task dependency assessment of a task dependency graph and task data requirements that correspond to each task of the plurality of tasks. Based on the task dependency assessment, the task scheduling unit schedules a first task of the plurality of tasks and a second proxy object of a plurality of proxy objects specified by the task data requirements such that a memory transfer of the second proxy object of the plurality of proxy objects occurs while the first task is being executed.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Muhammad Amber Hassaan, Anirudh Mohan Kaushik, Sooraj Puthoor, Gokul Subramanian Ravi, Bradford Beckmann, Ashwin Aji
  • Context partitioning of branch prediction structures
    Patent number: 11734011
    Abstract: A processor core executes a first process. The first process is associated with a first context tag that is generated based on context information controlled by an operating system or hypervisor of the processing system. A branch prediction structure selectively provides the processor core with access to an entry in the branch prediction structure based on the first context tag and a second context tag associated with the entry. The branch prediction structure selectively provides the processor core with access to the entry in response to the first process executing a branch instruction. Tagging entries in the branch prediction structure reduces, or eliminates, aliasing between information used to predict branches taken by different processes at a branch instruction.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marius Evers, David Kaplan
  • Compiler directed fine grained power management
    Patent number: 11726546
    Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vedula Venkata Srikant Bharadwaj, Shomit N. Das, Anthony T. Gutierrez, Vignesh Adhinarayanan
  • System and method for protecting GPU memory instructions against faults
    Patent number: 11726868
    Abstract: A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Michael Mantor, Sudhanva Gurumurthi
  • System and method for application migration for a dockable device
    Patent number: 11726926
    Abstract: Described is a method and apparatus for application migration between a dockable device and a docking station in a seamless manner. The dockable device includes a processor and the docking station includes a high-performance processor. The method includes determining a docking state of a dockable device while at least an application is running. Application migration from the dockable device to a docking station is initiated when the dockable device is moving to a docked state. Application migration from the docking station to the dockable device is initiated when the dockable device is moving to an undocked state. The application continues to run during the application migration from the dockable device to the docking station or during the application migration from the docking station to the dockable device.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jonathan Lawrence Campbell, Yuping Shen
  • Filtering micro-operations for a micro-operation cache in a processor
    Patent number: 11726783
    Abstract: A processor includes a micro-operation cache having a plurality of micro-operation cache entries for storing micro-operations decoded from instruction groups and a micro-operation filter having a plurality of micro-operation filter table entries for storing identifiers of instruction groups for which the micro-operations are predicted dead on fill if stored in the micro-operation cache. The micro-operation filter receives an identifier for an instruction group. The micro-operation filter then prevents a copy of the micro-operations from the first instruction group from being stored in the micro-operation cache when a micro-operation filter table entry includes an identifier that matches the first identifier.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marko Scrbak, Mahzabeen Islam, John Kalamatianos, Jagadish B. Kotra
  • Method and apparatus for a page-local delta-based prefetcher
    Patent number: 11726917
    Abstract: A method includes recording a first set of consecutive memory access deltas, where each of the consecutive memory access deltas represents a difference between two memory addresses accessed by an application, updating values in a prefetch training table based on the first set of memory access deltas, and predicting one or more memory addresses for prefetching responsive to a second set of consecutive memory access deltas and based on values in the prefetch training table.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Susumu Mashimo, John Kalamatianos
  • Distributed coherence directory subsystem with exclusive data regions
    Patent number: 11726915
    Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 15, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yasuko Eckert, Maurice B. Steinman, Steven Raasch
  • VRS RATE FEEDBACK
    Publication number: 20230252713
    Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 10, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Vineet Goel, Pazhani Pillai, Ruijin Wu, Christopher J. Brennan, Andrew S. Pomianowski
  • Dynamic kernel memory space allocation
    Patent number: 11720993
    Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 8, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Gutierrez, Muhammad Amber Hassaan, Sooraj Puthoor
  • Selective generation of miss requests for cache lines
    Patent number: 11720499
    Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 8, 2023
    Assignees: Advanced Micro Devices, Inc., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fataneh Ghodrat, Stephen W. Somogyi, Zhenhong Liu