Patents Assigned to Advanced Micro Devics, Inc.
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Patent number: 11763155Abstract: A system comprising an electronic device that includes a processor is described. During operation, the processor acquires a full version of a neural network, the neural network including internal elements for processing instances of input image data having a set of color channels. The processor then generates, from the neural network, a set of sub-networks, each sub-network being a separate copy of the neural network with the internal elements for processing at least one of the color channels in instances of input image data removed, so that each sub-network is configured for processing a different set of one or more color channels in instances of input image data. The processor next provides the sub-networks for processing instances of input image data—and may itself use the sub-networks for processing instances of input image data.Type: GrantFiled: August 12, 2019Date of Patent: September 19, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Abhinav Vishnu
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Patent number: 11762658Abstract: A processing unit such as a graphics processing unit (GPU) includes a plurality of vector signal processors (VSPs) that include multiply/accumulate elements. The processing unit also includes a plurality of registers associated with the plurality of VSPs. First portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. The multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. The accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.Type: GrantFiled: September 24, 2019Date of Patent: September 19, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Bin He, Michael Mantor, Jiasheng Chen, Jian Huang
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Publication number: 20230290400Abstract: A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.Type: ApplicationFiled: June 30, 2022Publication date: September 14, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Aaron D Willey, Karthik Gopalakrishnan, Ramon Mangaser
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Publication number: 20230290035Abstract: A system and method for performing graphics processing is provided. The system and method includes processing an allocation command for a buffer object; reserving processor address space for a data store of the buffer object with uncommitted physical memory in response to the allocation command including a null parameter, and reserving processor address space for a data store of the buffer object with committed physical memory in response to the allocation command including a non-null parameter.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
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Publication number: 20230289290Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: Advanced Micro Devices, Inc.Inventor: John Kelley
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Publication number: 20230289070Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
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Patent number: 11755494Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.Type: GrantFiled: October 29, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Paul J. Moyer
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Patent number: 11755477Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.Type: GrantFiled: December 28, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Chintan S. Patel, Girish Balaiah Aswathaiya
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Patent number: 11755246Abstract: A data processor includes a staging buffer, a command queue, a picker, and an arbiter. The staging buffer receives and stores first memory access requests. The command queue stores second memory access requests, each indicating one of a plurality of ranks of a memory system. The picker picks among the first memory access requests in the staging buffer and provides selected ones of the first memory access requests to the command queue. The arbiter selects among the second memory access requests from the command queue based on at least a preference for accesses to a current rank of the memory system. The picker picks accesses to the current rank among the first memory access requests of the staging buffer and provides the selected ones of the first memory access requests to the command queue.Type: GrantFiled: June 24, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
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Patent number: 11756606Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.Type: GrantFiled: December 13, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sriseshan Srikanth, Vignesh Adhinarayanan, Jagadish B. Kotra, Sergey Blagodurov
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Patent number: 11755336Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.Type: GrantFiled: September 29, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Todd Martin, Tad Robert Litwiller, Nishank Pathak, Randy Wayne Ramsey
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Patent number: 11757489Abstract: A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.Type: GrantFiled: December 8, 2021Date of Patent: September 12, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Ramon Mangaser, Karthik Gopalakrishnan, Andy Huei Chu, Pradeep Jayaraman
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Publication number: 20230280819Abstract: A method and system for operating in a single display mode operation and a dual pipe mode of operation is disclosed. The method and system includes operating in a dual pipe mode of operation in which each display pipe transmits data from a respective buffer to an associated display. The method and system further includes operating in a single display mode of operation in which one display pipe transmits data from a plurality of buffers to an associated display.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Alexander J. Branover, Christopher T. Weaver, Benjamin Tsien, Indrani Paul, Mihir Shaileshbhai Doctor, Thomas J. Gibney, John P. Petry, Dennis Au, Oswin Hall
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Publication number: 20230280906Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.Type: ApplicationFiled: November 7, 2022Publication date: September 7, 2023Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Xuan Chen, Ross V. La Fetra, Michael John Litt
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Patent number: 11748034Abstract: A memory controller selects from among a plurality of memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes. The selected memory access commands are transmitted to a heterogenous memory channel coupled to a non-volatile memory and a volatile memory. The non-volatile read commands that are transmitted are stored in a non-volatile command queue (NV queue). A ready response is received from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands. In response to receiving the ready response, a send command is transmitted for commanding the non-volatile memory to send the responsive data.Type: GrantFiled: August 23, 2021Date of Patent: September 5, 2023Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Kedarnath Balakrishnan
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Patent number: 11748186Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.Type: GrantFiled: April 4, 2022Date of Patent: September 5, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Andrew G. Kegel, David A. Roberts
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Patent number: 11747852Abstract: A method and apparatus for managing overclocking in a data center includes determining a frequency limit of a first processor of a first server in the data center. The voltage of the first processor is lowered to a stability point, and the frequency is lowered. The first server is tested for stability. Based upon the results of the test, the voltage and frequency modifications are deployed to a second processor of a second server in the data center.Type: GrantFiled: December 23, 2019Date of Patent: September 5, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Amitabh Mehra, Jeffrey N. Burley, Anil Harwani
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Patent number: 11748935Abstract: A technique for performing ray tracing operations is provided. The technique includes initiating bounding volume hierarchy traversal for a ray against geometry represented by a bounding volume hierarchy; identifying multiple nodes of the bonding volume hierarchy for concurrent intersection tests; and performing operations for the concurrent intersection tests concurrently.Type: GrantFiled: December 18, 2020Date of Patent: September 5, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Ruijin Wu
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Patent number: 11740791Abstract: In some embodiments, a memory controller in a processor includes a base value cache, a compressor, and a metadata cache. The compressor is coupled to the base value cache and the metadata cache. The compressor compresses a data block using at least a base value and delta values. The compressor determines whether the size of the data block exceeds a data block threshold value. Based on the determination of whether the size of the compressed data block generated by the compressor exceeds the data block threshold value, the memory controller transfers only a set of the compressed delta values to memory for storage. A decompressor located in the lower level cache of the processor decompresses the compressed data block using the base value stored in the base value cache, metadata stored in the metadata cache and the delta values stored in memory.Type: GrantFiled: October 8, 2021Date of Patent: August 29, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Seyed Mohammad Seyedzadehdelcheh, Xianwei Zhang, Bradford Beckmann, Shomit N. Das
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Patent number: 11741658Abstract: A frustum bounds a subset of rays projected into a virtual scene to be rendered. The frustum is transformed from a Cartesian coordinate space to a spherical coordinate space using a transform matrix that places a central ray of the frustum as the Z-axis. A projection hemisphere centered around the central ray is defined. The extents of the intersection of the transformed frustum and the surface of the projection hemisphere are bound by a frustum circle. A geometric object in the scene or a bounding volume is bound by a bounding sphere, which is transformed into the spherical coordinate system using the transform matrix, and then projected onto the surface of the projection sphere to define a bounding circle. The frustum is identified as intersecting the geometric object or bounding volume responsive to angular overlap and distance overlap between the frustum circle and the bounding circle.Type: GrantFiled: December 28, 2021Date of Patent: August 29, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Konstantin Igorevich Shkurko
