Patents Assigned to Advanced Micro Devics, Inc.
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Patent number: 11720328Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.Type: GrantFiled: September 23, 2020Date of Patent: August 8, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Bin He, Shubh Shah, Michael Mantor
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Publication number: 20230244751Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.Type: ApplicationFiled: April 7, 2023Publication date: August 3, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Shaizeen Aga, Nuwan Jayasena, Allen H. Rush, Michael Ignatowski
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Patent number: 11715183Abstract: Methods and apparatuses are disclosed herein for performing tone mapping and/or contrast enhancement. In some examples, a block mapping curve is low-pass filtered with block mapping curves of surrounding blocks to form a smoothed block mapping curve. In some examples, overlapped curve mapping of block mapping curves, including smoothed block mapping curves, is performed, including weighting, based on a pixel location, block mapping curves of a group of blocks to generate an interpolated block mapping curve and applying the interpolated block mapping curve to a pixel to perform ton mapping and/or contrast enhancement.Type: GrantFiled: June 1, 2022Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Ying-Ru Chen
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Patent number: 11715514Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.Type: GrantFiled: June 25, 2021Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Russell J. Schreiber, John J. Wuu
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Patent number: 11715253Abstract: A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.Type: GrantFiled: June 14, 2021Date of Patent: August 1, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Ruijin Wu, Skyler Jonathon Saleh, Christopher J. Brennan, Kei Ming Kwong, Anthony Hung-Cheong Chan
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Patent number: 11714652Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.Type: GrantFiled: July 23, 2021Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Ganesh Dasika
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Patent number: 11714442Abstract: An electronic device includes an accelerated processing unit (APU) and multiple elements. The APU performs operations for a platform boost and throttle (PBT) controller. For the operations, the APU receives a platform electrical power limit, the platform electrical power limit being a limit on a total electrical power allowed to be consumed by a group of the elements at a given time. The APU then determines a present platform electrical power consumption. The APU next adjusts one or more operating parameters for specified elements from among the group of elements to control electrical power consumption by the specified elements based on a relationship between the present platform electrical power consumption and the platform electrical power limit.Type: GrantFiled: December 23, 2021Date of Patent: August 1, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices Inc.Inventors: Meeta Surendramohan Srivastav, Ashwini Chandrashekhara Holla, Alex Sabino Duenas, Xinzhe Li, Michael John Austin, Indrani Paul, Sriram Sambamurthy
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Patent number: 11714559Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.Type: GrantFiled: September 25, 2020Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Michael W. LeBeane, Khaled Hamidouche, Hari S. Thangirala, Brandon Keith Potter
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Patent number: 11714739Abstract: A system and method for processing application performance using application phase differentiation and detection is disclosed. Phase detection may be accomplished in a number of different ways, including by using a deterministic algorithm that looks for changes in the computing resource utilization patterns (as detected in the performance data collected). Machine learning (ML) and neural networks (e.g. sparse auto encoder SAE) may also be used. Performance data is aggregated according to phase and stored in a database along with additional application and computing system information. This database may then be used to find similar applications for performance prediction.Type: GrantFiled: August 17, 2021Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Max Alt, Gabriel Martin, Paulo Roberto Pereira de Souza filho
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Patent number: 11715262Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.Type: GrantFiled: December 17, 2018Date of Patent: August 1, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Brian J. Favela, Todd Martin, Mangesh P. Nijasure
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Patent number: 11711571Abstract: A server offloads graphics effects processing to a client device with graphics processing resources by determining a modification to a graphics effects operation, generating a portion of a rendered video stream using the modification to the graphics effects operation, and providing an encoded representation of the portion of the rendered video stream to the client device, along with metadata representing the modification implemented. The client device decodes the encoded representation to recover the portion of the rendered video stream and selectively performs a graphics effects operation on the recovered portion to at least partially revert the resulting graphics effects for the portion to the intended effects without the modification implemented by the server.Type: GrantFiled: March 5, 2021Date of Patent: July 25, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Ihab Amer, Guennadi Riguer, Thomas Perry, Mehdi Saeedi, Gabor Sines, Yang Liu
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Patent number: 11710698Abstract: A layout for a 6T SRAM cell array is disclosed. The layout doubles the number of bits per bit cell in the array by implementing dual pairs of bitlines spanning bit cell columns in the array. Alternating connections (e.g., alternating vias) may be provided for wordline access to the bitlines in the layout. Alternating the connections may reduce RC delay in the layout.Type: GrantFiled: September 24, 2020Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John J. Wuu, Richard T. Schultz
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Patent number: 11709536Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.Type: GrantFiled: September 23, 2020Date of Patent: July 25, 2023Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Greg Sadowski, Sriram Sundaram, Stephen Kushnir, William C. Brantley, Michael J. Schulte
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Patent number: 11709681Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.Type: GrantFiled: December 11, 2017Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Jay Fleischman, Michael Estlick, Michael Christopher Sedmak, Erik Swanson, Sneha V. Desai
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Patent number: 11709711Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.Type: GrantFiled: December 13, 2020Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Guhan Krishnan
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Patent number: 11710207Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.Type: GrantFiled: March 30, 2021Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Christopher J. Brennan, Nishank Pathak
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Patent number: 11709670Abstract: An electronic device includes a processor and a storage device having a file system with a plurality of directories. The processor executes an application that has a dependency on a shared library, the shared library having a dependency on a runtime component. When executing the application, the processor loads the shared library, the loading including executing a constructor for the shared library. Executing the constructor causes the processor to identify a selected directory where a compatible version of the runtime component is to be found based on a location of the shared library in the file system, the location of the shared library being determined from an application context from the application. When subsequently loading the runtime component for execution, the processor locates the runtime component in the selected directory.Type: GrantFiled: April 14, 2020Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Srinivasan Subramanian, Pruthvi K. Madugundu, Freddy Paul, Jagadish Krishnamoorthy, Diwakar Das, Praveen K. Jain
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Patent number: 11709745Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.Type: GrantFiled: January 31, 2022Date of Patent: July 25, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Michael Ignatowski, Vilas Sridharan
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Patent number: 11704248Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.Type: GrantFiled: November 6, 2020Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventors: William L. Walker, Michael L. Golden, Marius Evers
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Patent number: 11704250Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.Type: GrantFiled: September 28, 2021Date of Patent: July 18, 2023Assignee: Advanced Micro Devices, Inc.Inventor: Paul J. Moyer
