Abstract: An apparatus and method for efficiently scheduling instructions for a parallel data processing circuit. In various implementations, a computing system includes a parallel data processing circuit with multiple compute circuits, each uses multiple single instruction multiple data (SIMD) circuits. Each compute circuit includes a scheduler for selecting instructions to issue to the SIMD circuits. During execution, a thread executes an instruction that provides a point of synchronization. Examples are the wait instruction and the barrier instruction. A control circuit accesses the metrics indicating hardware behavior of the corresponding wave. Based on these metrics, the control circuit generates a prediction of the amount of time before the point of synchronization completes. For example, the prediction indicates how soon each of the other threads of the corresponding wave are to arrive at the point of synchronization. The prediction is used to update control flow of the thread.

Abstract: An input/output memory management unit includes a control logic circuit and a device table entry valid bit array. The control logic circuit provides physical addresses in response to virtual addresses of memory access requests from a plurality of input/output devices. The device table entry valid bit array stores a plurality of valid bits corresponding to different ones of the plurality of input/output devices. The control logic circuit accesses a first valid bit corresponding to a first input/output device from the device table entry valid bit array, and selectively accesses a device table in a system memory in response to a state of the valid bit.

Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent is for generating memory access requests for a memory. The memory controller includes a command queue and a refresh controller. The command queue is for storing the memory access requests. The refresh controller is coupled to the command queue and is operable to select an order of providing same bank refresh commands to a plurality of refresh groups of corresponding banks in the memory based on an aggregate request count of the memory access requests in the command queue.

Abstract: The disclosed systems and methods provide signal crossing across die boundaries of stacked dies. By having a queue structure coupled to a multiplexer hierarchy, clock skew and other differences between stacked dies can be addressed without require a prohibitive number of TSVs, BPVs, or other vertical interconnects. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An implementation is a method for operating a cache memory in a computing system, receiving a request for a first data item from the cache memory of the computing system, the first data item having an associated tag value. The method also includes performing a lookup in a bloom filter for the tag value associated with the first data item. The method also includes performing a lookup in the cache memory for the requested first data item based on the lookup in the bloom filter. The method also includes updating the bloom filter based on results of the lookup in the cache memory for the requested first data item.

Abstract: The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A device that defines and uses a bounding volume for testing for ray intersections with a displaced micro-mesh. The bounding volume is indirectly based on a twisted prism composed of two triangles and three bilinear patches that bounds the displaced micro-mesh. Instead of detecting intersection with the bilinear patches directly, tetrahedrons that circumscribe the bilinear patches can be used instead. The two bases and the three tetrahedra make fourteen triangles. The device tests for potential intersection with the displaced micro-mesh by testing for an intersection with any of the fourteen triangles. Various other methods and systems are also disclosed.

Abstract: In accordance with the described techniques, a command processor processes a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between tasks within the fibers. As part of this, the command processor dispatches a task from a fiber for execution by a processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved. While the task is dispatched and unexecuted by the processing element array, the command processor enqueues the fiber in a sleep queue. Further, the command processor enqueues the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array. Based on the fiber being in the check queue, the command processor enqueues a dependent fiber in the ready queue that depends from the fiber.

Abstract: A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.

Abstract: A processing system preconditions block-compressed texture blocks by separately streaming color components and index components for lossless compression. The processing system preconditions the color components for linear compression, such that color component data for adjacent compressed blocks in a row are further compressed using lossless compression. Lossless compression is performed for color components spanning multiple rows to leverage patterns in color components that extend vertically across a frame. The processing system further divides input color component and index component data into pages of memory (e.g., 64 kB pages), such that each page can be independently losslessly compressed and decompressed. The processing system applies delta encoding to color component data so that a single instance of color data and differences from the stored color data are stored for each page.

Abstract: A distributed processing system includes one or more accelerated units (AUs) connected to a network. To control access to the AUs by one or more users over the network, the distributed processing system includes a control plane circuitry connected to the network. The control plane circuitry is configured to grant a user access to one or more AUs connected to the network based on user security data stored at the control plane circuitry. The security data stored at the control plane circuitry indicates which resources of one or more AUs connected to the network one or more users are authorized to access.

Abstract: A processor includes two or more core dies each including one or more processor cores and/or associated with one or more input/output dies. A hypervisor, firmware in a central processing unit (CPU), or software or firmware located outside of the CPU assigns virtual machines or threads to a first core die and disconnects power from a second core die with no active threads or cores, e.g., by adjusting one or more voltage regulators associated with the second core die, while still providing power to the first core die. In some implementations, active threads or processing cores are migrated from sparsely allocated processing cores or core dies into a reduced number of core dies. Power usage is minimized by disconnecting one or more inactive core dies from power while performance is maximized by increasing the clock frequency of remaining active core dies or remaining active processing cores located therein.

Abstract: The disclosed method includes waveform extractions from a cross-talking environment by measuring a signal from a target circuit/transistor while deterministically stimulating a second circuit using a second laser and post-processing. The method includes analyzing the measured signal detecting a fault or an error in one of the circuits based on the analysis. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In some implementations, the device may include detecting a speculative load hardening indicator in a first block of code. In addition, the device may include selectively suppressing hardware speculative execution for instructions in the first block of code associated with the detected speculative load hardening indicator.

Abstract: Techniques for performing machine learning operations are provided. The techniques include configuring a first portion of a first chiplet as a cache; performing caching operations via the first portion; configuring at least a first sub-portion of the first portion of the chiplet as directly-accessible memory; and performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet.

Abstract: Systems, methods, and devices for determining a derived counter value based on a hardware performance counter. Example devices include input circuitry configured to input a hardware performance counter value; counter engine circuitry configured to determine the derived counter value by applying a model to the hardware performance counter value; and output circuitry configured to communicate the derived counter value to a consumer. In some examples, the consumer includes an operating system scheduler, a memory controller, a power manager, or a data prefetcher, or a cache controller. In some examples, the processor includes circuitry configured to dynamically change the model during operation of the processor. In some examples, the model includes or is generated by an artificial neural network (ANN).

Abstract: A processing unit manages temperature by correlating readings from a plurality of external temperature sensors to a skin temperature of the processing unit, wherein the correlation is based on characteristics of a computer chassis that is to include the processing unit. The processing unit is mounted on a printed circuit board (PCB) or other substrate that is to be placed in a computer chassis. Each of a plurality of temperature sensors is placed at a different location of the PCB to provide temperature readings from a variety of locations of the PCB. A temperature controller of the processing unit receives temperature readings from the plurality of sensors and correlates the temperature readings with a skin temperature of the processing unit based on a plurality of correlation values.

Abstract: A processing system includes one or more network-attached hostless accelerator (NAHA) units each having an integrated circuit. The integrated circuit of each NAHA unit includes a memory and a first network interface controller configured to communicatively couple the memory to a network such that the memory of the NAHA unit is communicatively coupled to one or more memories of other NAHA units via the network. Additionally, a NAHA unit of the processing system includes one or more processor cores configured to execute an instruction to generate a result. Further, the one or more processor cores of the NAHA unit are configured to store the result in the one or more memories of the other NAHA units.

Abstract: A data processor includes a memory accessing agent for generating memory access requests for a memory that includes a plurality of banks, and a memory controller. The memory controller includes a command queue and a refresh controller. The command queue is for storing the memory access requests. The refresh controller is coupled to the command queue and is operable to select an order of providing multi-bank refresh commands to sets of selected banks of the plurality of banks in the memory in response to lowest-cost estimates of the banks of the memory based on the memory access requests in the command queue.

Abstract: Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).