Abstract: Systems and methods for reducing, by a link partner, backlog at a receiver buffer of the other link partner. Each link partner includes at least one circuit coupled between a data fabric and an interconnect link of an interconnect fabric. The at least one circuit includes a receiver configured to receive datagrams from the interconnect fabric and a transmitter configured to send datagrams over the interconnect fabric. The transmitter is configured to monitor a loop latency for datagrams communicated between the link partners over the interconnect fabric using toggling handshake codes in their headers. Based on the monitored loop latency for the datagrams, the transmitter of a link partner is configured to reduce a receiver buffer backlog at the other link partner. The loop latency monitoring can include monitoring an unloaded and loaded loop latencies and comparing a difference between the loop latencies to one or more thresholds.

Abstract: Systems and devices for packing one or more sequence numbers into datagrams for transmission to a link partner over an interconnect fabric, the link partners including a transmitter in communication with a receiver for data transmission over the interconnect link, each of the transmitter and the receiver including at least one circuit. The at least one circuit packages a header and a data payload into data packets for transmission to the other of the transmitter and the receiver. Responsive to a request from the transmitter or the receiver, the at least one circuit of the transmitter or the receiver encodes a first sequence number and a second sequence number into the header of the data packet for transmission to the other of the transmitter or the receiver. The first sequence number may be a transmitter sequence number, and the second sequence number may be a receiver sequence number.

Abstract: Systems and devices for Universal Asynchronous Receiver Transmitter (UART) mode communication may include a first circuit including a first receiver transmitter in communication with a second receiver transmitter of a second circuit over an interconnect link. In a transmit direction, the first circuit is configured to pack stream transport data into data flits of a datagram for serialized transmission of data from the first receiver transmitter to the second receiver transmitter over the interconnect link. In a receive direction, the first circuit is configured to unpack the stream transport data from the data flits received as serialized data over the interconnect link from the second circuit of the second receiver transmitter. The stream transport data can be firmware data packed into the data flits as data link messages, which may be exchanged between firmware agents associated with the respective first circuit and second circuit.

Abstract: Systems and devices for packaging first data flits into second data flits may include at least one circuit of a first processor. In a transmit direction, the at least one circuit receives first data flits and packages the data of the first data flits into second data flits for transmission to at least one second processor over an interconnect link. In a receive direction, the at least one circuit receives a second data flit and packages the data into one or more first data flits for transmission to the first processor. The first data flit and second data flit may be a transaction layer flit and data layer flit, respectively. The second data flit may include a flit header, a cyclic redundancy check, and a plurality of segments, each segment including a segment header, an integer number of sectors, and one or more portions for storing the first data flits.

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

Abstract: An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.

Abstract: In accordance with described techniques for process optimized routing fabric in a stacked die, a stacked dies includes a static random-access memory (SRAM) die, and a compute die in a stacked orientation with the SRAM die. The stacked die also includes a routing fabric implemented on the SRAM die, and the routing fabric processes data routing and distributes the data across the stacked die.

Abstract: The present disclosure relates to systems and methods for memory dependency prediction. The systems and methods include maintaining, by processing circuitry, a set of store instructions recently dispatched for execution, each store instruction having a type and one or more attributes and in response to a load instruction that has a first type and a first set of one or more attributes that corresponds to a type and attributes for a store instruction in the set of store instructions recently dispatched for execution, indicating, by the processing circuitry, a memory dependency between the load instruction and the store instruction.

Abstract: In ray tracing hardware, dedicated circuitry is often used to traverse a bounding volume hierarchy. This dedicated hardware has an internal memory that stores state for rays for which such traversal is being performed. If this internal memory becomes full with outstanding rays, the dedicated hardware may become starved of work. For this reason, techniques are provided to “overflow” rays from this internal memory a hit buffer. Slots in the hit buffer can be used for two different purposes—to store information about detected hits, as well as to store working state for rays outstanding in the dedicated intersection hardware. If this dedicated hardware receives work that does not fit in its internal memory, the dedicated intersection hardware stores such work into the hit buffer. When slots become free in the internal memory, the intersection hardware retrieves such work from the hit buffer for processing.

Abstract: An integrated circuit can include one or more metal layers having one or more interconnects and a metal insulator metal (MIM) capacitor disposed between the metal layers. In some examples, the MIM capacitor can include one or more conductive plates with insulating layers disposed between the conductive plates. In some examples, a plurality of vias can connect the one or more metal layers and the one more conductive plates. In some examples, at least some of the vias do not extend through the entire depth of the MIM capacitor. For example, at least some of the vias can terminate at a conductive plate rather than extend from a first metal layer through one or more conductive plates to a second metal layer. In some examples, the MIM capacitors can realize high capacitance density and low impedance.

Abstract: A method for dynamically switching between branch prediction modes may include evaluating a criterion associated with dynamic selection of a mode of speculative prediction of outcomes of one or more branch instructions, wherein the criterion is based on addresses of a plurality of branch instructions executed during a first time period. The method may also include initiating, during a second time period, the mode of speculative prediction of outcomes of the one or more branch instructions, wherein the mode of the speculative prediction is selected based, at least in part, on the criterion.

Abstract: In some compression formats, individual items of compressed data have a variable size such that it is not straightforward to be able to determine where a particular item of compressed data is. One example of such a compression format represents a mesh of triangles as a set of compression blocks, where each block can have a different number of triangles. A technique is provided herein to perform a lookup that involves dividing the triangles in the set of compression blocks into fixed-size groups, each having corresponding metadata. The metadata includes location information for the first triangle of the group and a mask that indicates, for each triangle, whether that triangle is at the end of a compression block. Using this information, a decompressor performs bookkeeping operations to calculate which compressed block a triangle is in and which slot in that compressed block stores the information for that triangle.

Abstract: Data transfer for heterogenous memory systems is described. In one or more implementations, a data transfer device includes a controller and transfer logic. The controller receives a data transfer request from a processor and, responsive to the request, obtains data from a source memory location and transfers data to a destination memory location. During the transfer, the transfer logic performs at least one data transfer operation in relation to the data to optimize the transfer. Examples of data transfer operations include controlling data access order, rearranging the data, and modifying the data.

Abstract: Methods, apparatus, and computer-readable media for executing operations on single-instruction-multiple-data (SIMD) units. A lane of a wave executing on a SIMD unit executes a dot-product instruction during a clock cycle of the lane using operands stored in vector general purpose registers (VGPRs) of the lane. The dot-product instruction generates a convolution result for a data element of input data and applies one or more transitional operations to the convolution result to generate an output data element. The transitional operations include any one or any combination of a reformatting operation, a rectifying operation, and a clamping operation. The dot-product instruction may be a dual dot-product instruction that generates convolution results for two data elements and applies the transitional operations to produce two output data elements during the clock cycle of the lane.

Abstract: The disclosed device includes a base die and one or more stack die, and includes various components that facilitate power management for the device. The device, for example, includes a clock driver that drives a clock signal for propagation through a clock distribution tree for delivery to one or more components of the one or more stack die. A controller of the device triggers an operation on the one or more stack die and generates a stack die activity prediction based on the triggered operation. A clock gater of the device gates the clock signal for at least a portion of the clock distribution tree based on the stack die activity prediction. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: In accordance with the described techniques, a device includes a plurality of processor cores, each associated with a cache system, and a cache controller configured to receive memory access requests to the cache system from the plurality of processor cores. The device also includes a directory communicatively coupled to the cache controller and configured to receive a self-invalidating lookup command from the cache controller caused by a request to update a cache line. The directory is further configured to perform a lookup operation to identify a processor core having a copy of the cache line, initiate one or more invalidation sequences for each processor core having a copy of cache line, and update cache line states to reflect invalidation of the cache line.

Abstract: Devices, systems, and methods for direct cache injection. An example device issues a coherent write request over a cache-coherent memory protocol channel, including a data payload and a device-initiated request packet. The device adds a cache resource identifier in the request packet, providing a steering hint for directing the data payload to a caching resource in the host system. The device sets a locality hint in the request packet, the locality hint indicating one or more access characteristics of the data payload. The data payload is directed to the caching resource based on the cache resource identifier and the temporal locality hint. An example system may further include a device driver that programs the cache resource identifier based on host system topology information and dynamically updates the cache resource identifier based on changes in software scheduling.

Abstract: Techniques are provided herein to provide a customized set of shader programs for different hardware versions for ray tracing hardware. Each such shader program varies in terms of what local state is stored. In particular, each shader program is tailored such that its associated set of local state does not exceed the amount actually needed by the corresponding hardware version. This customization of shader programs helps to reduce the amount of resources utilized by the shader programs, as compared with a situation in which a single “monolithic” shader program checked the hardware version at runtime, as such a monolithic shader program would need to reserve the maximum amount of resources for any possible hardware version.

Abstract: A system can include an integrated circuit; and an adaptive voltage regulator (AVR) device configured to provide a power supply signal having a regulated voltage to the integrated circuit. The AVR can include a slew rate control circuit configured to perform operations including adjusting a maximum slew rate of the regulated voltage based on an amplitude of a load current provided to the integrated circuit (IC). In some examples, the AVR improves the performance of the IC by responding rapidly to changes in the IC's target supply voltage when the load current is relatively low, while also limiting the occurrence of potentially harmful over-currents by lowering the slew rate of the regulated supply voltage when the load current is already relatively high.

Abstract: Techniques for performing machine learning operations are provided. The techniques include configuring a first portion of a first chiplet as a cache; performing caching operations via the first portion; configuring at least a first sub-portion of the first portion of the chiplet as directly-accessible memory; and performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet. In some examples, the first and second chiplets are separate dies. In some examples, the caching operations include one or more of storing a cache line evicted from a cache of the processing core or providing a cache line to the processing core in response to a miss in a cache of the processing core.