Abstract: A processing system receives graph object data and graph object metadata. The processing system stores the graph object metadata inline with the graph object data. The graph object metadata indicates access permissions for corresponding graph objects. Because the graph object metadata is stored inline with the graph object data, the graph object metadata is more easily retrieved and fewer system resources are consumed to determine access permissions of a requester as compared to a system where graph object metadata is stored separately from the graph object data.

Abstract: Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.

Abstract: Embodiments herein describe tracking the number of congested paths in a multipath connection between endpoints to determine when to throttle the data being transmitted by a sender. In one embodiment, the embodiments herein permit a sender to determine whether congestion is caused by the receiver (or the network as a whole) being congested or only a few paths in the network being congested. The receiver may provide congestion signals that indicate congested paths as feedback to the sender. The sender can track the number of congested paths. For example, the sender can determine a ratio between the number of congested paths and the total paths in the multipath connection. Once this ratio reaches a threshold, the sender may begin data throttling. However, until then, the sender may redirect data that would have been sent on the congested paths to paths that are not yet congested.

Abstract: A masked atomic update instruction is described that atomically performs compare and exchange operations on select bits of a data structure. Executing the masked atomic update instruction compares respective source values with respective values of bits stored at a destination data storage location. If the respective bit values match, one or more of the respective bit values at the destination are replaced with one or more defined replacement values. Alternatively, if the respective bit values do not match, the destination is not modified. The masked atomic update instruction enables a processing unit to mask out bits of the destination data storage location that are not involved in the comparison or update. The masked atomic update instruction thus provides bit-level granularity by which another thread is prevented from accessing bits of the destination data storage location. This bit-level granularity advantageously permits multiple threads to simultaneously access a common data storage location.

Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.

Abstract: Keyword-based device activation to avoid false positives includes detecting, by a hardware processor of a device, a first user utterance specifying a first keyword of a multi-keyword phrase from audio data. In response to detecting the first user utterance, the audio data is monitored by the processor for a second user utterance specifying a second keyword of the multi-keyword phrase, and sensor data generated by a user attention sensor of the device is monitored for an indication of user attention directed to the device. In response to detecting the second keyword and detecting the indication of user attention directed to the device, a selected operation of the device is initiated by the hardware processor.

Abstract: In-system electrical connectivity detection. In one or more implementations, a computing device includes a transmitter and a receiver in a package, the transmitter to transmit a signal to a separate device, the receiver to receive and measure a reflection of the transmitted signal, and the measured reflection for characterizing (e.g., testing or detecting) an electrical connection between the computing and separate devices. The computing device may characterize (e.g., detect a discontinuity in) the electrical connection by comparing a magnitude of the transmitted signal with a magnitude of the measured reflection. The computing device may be coupled with the separate device by multiple electrical connections, and the multiple electrical connections may be tested by corresponding transmitters and receivers.

Abstract: Methods and systems are disclosed for executing operations on single-instruction-multiple-data (SIMD) units. Techniques disclosed perform a dot product operation on input data during one computer cycle, including convolving the input data, generating intermediate data, and applying one or more transitional operations to the intermediate data to generate output data. Aspects described, wherein the input data is an input to a layer of a convolutional neural network and the generated output data is the output of the layer.

Abstract: A system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.

Abstract: Supply chain security for chiplets is described. In accordance with the described techniques, a chiplet manufacturing interface obtains first test results, and stores an encrypted version of the first test results in a database accessible by the chiplet manufacturing interface and a chiplet integration interface. The chiplet integration interface obtains second test results from at least one chiplet, retrieves, from the database, the encrypted version of the first test results, decrypts the encrypted version of the first test results to obtain a first hash of the first test results, and selectively integrates the at least one chiplet into an integrated circuit based on a comparison of the first test results and the second test results and a comparison of the first hash and a second hash of the second test results generated by the chiplet integration interface.

Abstract: A technique is provided. The technique includes identifying memory cells, of a set of memory cells to power down, based on a set of priorities for the set of memory cells; powering down the identified memory cells in accordance with the set of priorities, resulting in powered down memory cells; and performing processing in accordance with the powered down memory cells.

Abstract: A system and method for using an operation (op) cache is disclosed. The system and method include an op cache for caching previously decoded instructions. The op cache includes a plurality of physically indexed and tagged instructions allowing sharing of instructions between threads. The op cache is chained through multiple ways allowing service of a plurality of instructions in a cache line. The op cache is stored between a shared operation storage and immediate/displacement storage to maximize capacity.

Abstract: A disclosed system can include (i) a data consumer, (ii) a data producer, and (iii) a virtual channel enabled credit repeater pipeline that connects the data consumer and the data producer across at least both a guaranteed track and an opportunistic track. The virtual channel enabled credit repeater pipeline at the data producer can forward virtual channel data across the opportunistic track based on an amount of credits being insufficient. Various other methods, systems, and apparatuses are also disclosed.

Abstract: A parallel processor assigns data for use by one or more tasks to a shared memory or memories associated with a plurality of compute units. A scheduler or other controller within or otherwise associated with the parallel processor assigns threads or groups of threads, which utilize the assigned data, to compute units as appropriate. Compute units utilize two sets of instructions, one specifying upper bits and one specifying lower bits of a memory address, to specify memory addresses that are larger than a number of bits an individual instruction can specify in a memory address field. Mode setting commands determine when and how lower bits in a memory address field of an instruction will be combined with upper bits in a previous instruction, e.g., through concatenation.

Abstract: A processing unit performs a dispatch walk of a set of thread groups based on a programmable access pattern. The access pattern is stored at a table that is programmed with the access pattern based upon a specified command. By using the command to program the table with different access patterns, the dispatch order of the set of thread groups is adapted to better suit the processing of different data sets, thereby reducing power consumption at the processing unit, and improving overall processing efficiency.

Abstract: Hardware processor-based data compression includes subdividing source data into a plurality of partitions. A partition size for the subdividing is selected based on a search window size of a compression technique and a cache size of the hardware processor. A number of the plurality of partitions is selected based, at least in part, on a size of the source data and the partition size. Compressed data is generated by the hardware processor by performing multi-threaded compression in which a plurality of threads execute the compression technique on the plurality of partitions in parallel. Some aspects include prepending a random-access point (RAP) metadata frame by multi-threaded compression at a start of the plurality of partitions to enable the multi-threaded and parallel decompression. The RAP metadata frame is interpretable to enable single-threaded decompression by legacy decompressors.

Abstract: A method, system, and computer-readable medium for executing a task is disclosed. The method includes receiving input data and computing instructions, launching a workgroup including wavefronts to execute the task, wherein the launching causes the wavefronts to process the input data by sharing intermediate results and resources, and adjusting the operation based on characteristics of the wavefronts. The characteristics include data dependencies, computational load, memory usage, and execution timing requirements. The wavefronts execute the task in stages, where each stage processes portions of input data and data generated by other wavefronts.

Abstract: Data integrity checks for reducing communication latency is described. A transmitting endpoint transmits data to a receiving endpoint by generating an integrity tag for a first subset of data blocks and a second integrity tag for a second subset of data blocks. In implementations, the first and second integrity tags overlap at least one data block and are offset based on computational complexities of generating the integrity tags. A receiving endpoint generates comparison tags for each of the integrity tags and uses the comparison tags to validate an authenticity of received data. In response to validating the first and second integrity tags, data blocks covered by both the first and second integrity tags are released for use. Additional integrity tags are generated and validated for subsequent subsets of data blocks during data communication, thus reducing latency by offsetting times at which comparison tags are generated and validated.

Abstract: A processing system stores a boot image for a critical domain of a system-on-a-chip (SOC) at a bank of a static random-access memory (SRAM) that is shared by the critical domain and a non-critical domain and that is powered independently from the non-critical domain. The SOC includes a secure processor that loads the boot image to the bank of the SRAM and then blocks subsequent write access to the bank. Because the critical domain is powered independently from the non-critical domain, the bank of the SRAM retains the boot image without regard to the power state of the non-critical domain. In addition, the critical domain implements a boot process that is decoupled from a CPU at the non-critical domain, ensuring that the critical domain can initiate a re-boot sequence even if the non-critical domain is not powered.

Abstract: Parallel-split all-to-all data communication is described. An average latency between ranks among which data blocks are to be exchanged is estimated. A split factor is then derived based on the estimated rank-to-rank latency, a number of ranks involved in the all-to-all operation, as well as a size of a data block communicated between ranks. A parallel-split all-to-all system divides the ranks into a number of parallel groups defined by the split factor. Within each group, a linear all-to-all communication is performed. Once the parallel groups have completed their internal all-to-all communication, the parallel-split all-to-all system reorganizes the ranks into exchange groups using split factor. The parallel-split all-to-all system completes the all-to-all data transfer by causing ranks to exchange data blocks among one or more other ranks included in their respective exchange group.