Abstract: Systems, apparatuses, and methods for implementing defogging techniques for images and video are disclosed. A defogging engine generates a defog filter result from a grayscale format version of an input image. An estimation engine generates an enhancement strength variable from a hue-saturation-value (HSV) format version of the input image. An enhancement engine receives both the defog filter result from the defogging engine and the enhancement strength variable from the estimation engine. The enhancement engine also receives the original red-green-blue (RGB) color space format version of the input image. The enhancement engine generates an enhanced version of the input image from the original RGB format version based on the defog filter result and the enhancement strength variable. The enhanced version of the input image mitigates fog, haze, mist or other environmental impediments that obscured the original input image.

Abstract: Embodiments herein describe generating packets that combine an atomic operation (e.g., an atomic fetch) with a data operation (e.g., a put). Previous remote atomics first transmit a packet to a remote node that provides a lock for the data. If the lock is granted, the node transmits another packet containing a data operation which can read or write data. However, the embodiments herein can use a relaxed range-based atomics where the packet uses a range to reserve space in a dataset (e.g., a buffer) at the destination node for the data operation.

Abstract: A host processing system assigns unequal time slices at a parallel processor to virtual functions based on profiles of applications executing at the virtual functions and an available budget of the parallel processor. The host processing system calculates a world switch cycle interval and assesses an available processing budget of the parallel processor. The available budget indicates the amount of graphics processing time the parallel processor has not yet allocated to virtual functions for each world switch cycle interval.

Abstract: Systems, apparatuses, and methods for optimizing a bounding volume hierarchy (BVH) are disclosed. A system selects a first node having an initial position in the BVH structure. The system determines a new position for the first node in the BVH structure and restructures the BVH structure by removal of the first node from the initial position and insertion of the first node in the new position to replace a second node. The restructured BVH is optimized using perturbation to achieve global surface area reduction.

Abstract: Integrated circuit (IC) memory devices and methods for fabricating the same are provided. In one example, an integrated circuit (IC) memory device is provided that includes a substrate, at least two or more memory (IC) dies, and a non-memory IC die integrated in a chip package. The memory (IC) dies are stacked on the substrate to form a memory die stack. The non-memory IC die contains row segmentation logic having an output routed to corresponding wordline drivers of the memory IC dies through vertical wiring passing through the memory die stack.

Abstract: Methods and devices are provided for processing data using a neural network. Activations from a previous layer of the neural network are received by a layer of the neural network. Weighted values, to be applied to values of elements of the activations, are determined based on a spatial correlation of the elements and a task error output by the layer. The weighted values are applied to the values of the elements and a combined error is determined based on the task error and the spatial correlation.

Abstract: An apparatus includes a storage location that is accessible to control plane circuitry and first circuitry configured to receive an interrupt indicating a fatal error. The first circuitry is also configured to provide, in response to the interrupt, first information indicating the fatal error to a data plane entity and second information indicating the fatal error to the storage location. The second information in the storage location is accessible via a control plane connection independently of the data plane entity initiating one or more recovery actions in response to receiving the first information. A system management controller (SMC) or a baseboard management controller (BMC) can be configured to access the second information in the storage location and convey the second information to control plane circuitry in a data center.

Abstract: Systems and methods for reducing, by a link partner, backlog at a receiver buffer of the other link partner. Each link partner includes at least one circuit coupled between a data fabric and an interconnect link of an interconnect fabric. The at least one circuit includes a receiver configured to receive datagrams from the interconnect fabric and a transmitter configured to send datagrams over the interconnect fabric. The transmitter is configured to monitor a loop latency for datagrams communicated between the link partners over the interconnect fabric using toggling handshake codes in their headers. Based on the monitored loop latency for the datagrams, the transmitter of a link partner is configured to reduce a receiver buffer backlog at the other link partner. The loop latency monitoring can include monitoring an unloaded and loaded loop latencies and comparing a difference between the loop latencies to one or more thresholds.

Abstract: Systems and devices for packing one or more sequence numbers into datagrams for transmission to a link partner over an interconnect fabric, the link partners including a transmitter in communication with a receiver for data transmission over the interconnect link, each of the transmitter and the receiver including at least one circuit. The at least one circuit packages a header and a data payload into data packets for transmission to the other of the transmitter and the receiver. Responsive to a request from the transmitter or the receiver, the at least one circuit of the transmitter or the receiver encodes a first sequence number and a second sequence number into the header of the data packet for transmission to the other of the transmitter or the receiver. The first sequence number may be a transmitter sequence number, and the second sequence number may be a receiver sequence number.

Abstract: Systems and devices for Universal Asynchronous Receiver Transmitter (UART) mode communication may include a first circuit including a first receiver transmitter in communication with a second receiver transmitter of a second circuit over an interconnect link. In a transmit direction, the first circuit is configured to pack stream transport data into data flits of a datagram for serialized transmission of data from the first receiver transmitter to the second receiver transmitter over the interconnect link. In a receive direction, the first circuit is configured to unpack the stream transport data from the data flits received as serialized data over the interconnect link from the second circuit of the second receiver transmitter. The stream transport data can be firmware data packed into the data flits as data link messages, which may be exchanged between firmware agents associated with the respective first circuit and second circuit.

Abstract: Systems and devices for packaging first data flits into second data flits may include at least one circuit of a first processor. In a transmit direction, the at least one circuit receives first data flits and packages the data of the first data flits into second data flits for transmission to at least one second processor over an interconnect link. In a receive direction, the at least one circuit receives a second data flit and packages the data into one or more first data flits for transmission to the first processor. The first data flit and second data flit may be a transaction layer flit and data layer flit, respectively. The second data flit may include a flit header, a cyclic redundancy check, and a plurality of segments, each segment including a segment header, an integer number of sectors, and one or more portions for storing the first data flits.

Abstract: A system and method for efficiently creating layout for memory bit cells are described. In various implementations, cells of a library use Cross field effect transistors (FETs) that include vertically stacked gate all around (GAA) transistors with conducting channels oriented in an orthogonal direction between them. The channels of the vertically stacked transistors use opposite doping polarities. A first category of cells includes devices where each of the two devices in a particular vertical stack receive a same input signal. The second category of cells includes devices where the two devices in a particular vertical stack receive different input signals. The cells of the second category have a larger height dimension than the cells of the first category.

Abstract: An apparatus and method for efficiently managing performance among replicated modules of an integrated circuit despite manufacturing variations across semiconductor dies. An integrated circuit includes a first module with a first partition of multiple dies that share at least a same first power rail. The integrated circuit also includes a second module with a second partition of multiple dies that share at least a same second power rail different from the first power rail. The dies within partitions have differences in circuit parameters within a threshold such that the dies can be placed in a same first bin. The dies in different partitions belong to different bins. A power manager initially assigns the same operating parameters to the first partition and the second partition, but adjusts the operating parameters based on detection of the different circuit behavior due to manufacturing variations between the first partition and the second partition.

Abstract: An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.

Abstract: An integrated circuit system includes voltage regulator circuitry that is coupled to and drives an integrated circuit device. The voltage regulator circuitry includes source follower circuitry, trans-impedance amplifier circuitry, and tracking circuitry. The source follower circuitry receives a first signal and generates a second signal by applying a first gain to the first signal. The trans-impedance amplifier circuitry receives the second signal from the source follower circuitry and outputs a third signal based on the second signal. The tracking circuitry receives the third signal from the trans-impedance amplifier circuitry and an output signal of the voltage regulator circuitry, and tracks a load current of the output signal using the third signal.

Abstract: In accordance with described techniques for process optimized routing fabric in a stacked die, a stacked dies includes a static random-access memory (SRAM) die, and a compute die in a stacked orientation with the SRAM die. The stacked die also includes a routing fabric implemented on the SRAM die, and the routing fabric processes data routing and distributes the data across the stacked die.

Abstract: In ray tracing hardware, dedicated circuitry is often used to traverse a bounding volume hierarchy. This dedicated hardware has an internal memory that stores state for rays for which such traversal is being performed. If this internal memory becomes full with outstanding rays, the dedicated hardware may become starved of work. For this reason, techniques are provided to “overflow” rays from this internal memory a hit buffer. Slots in the hit buffer can be used for two different purposes—to store information about detected hits, as well as to store working state for rays outstanding in the dedicated intersection hardware. If this dedicated hardware receives work that does not fit in its internal memory, the dedicated intersection hardware stores such work into the hit buffer. When slots become free in the internal memory, the intersection hardware retrieves such work from the hit buffer for processing.

Abstract: The present disclosure relates to systems and methods for memory dependency prediction. The systems and methods include maintaining, by processing circuitry, a set of store instructions recently dispatched for execution, each store instruction having a type and one or more attributes and in response to a load instruction that has a first type and a first set of one or more attributes that corresponds to a type and attributes for a store instruction in the set of store instructions recently dispatched for execution, indicating, by the processing circuitry, a memory dependency between the load instruction and the store instruction.

Abstract: An integrated circuit can include one or more metal layers having one or more interconnects and a metal insulator metal (MIM) capacitor disposed between the metal layers. In some examples, the MIM capacitor can include one or more conductive plates with insulating layers disposed between the conductive plates. In some examples, a plurality of vias can connect the one or more metal layers and the one more conductive plates. In some examples, at least some of the vias do not extend through the entire depth of the MIM capacitor. For example, at least some of the vias can terminate at a conductive plate rather than extend from a first metal layer through one or more conductive plates to a second metal layer. In some examples, the MIM capacitors can realize high capacitance density and low impedance.

Abstract: A method for dynamically switching between branch prediction modes may include evaluating a criterion associated with dynamic selection of a mode of speculative prediction of outcomes of one or more branch instructions, wherein the criterion is based on addresses of a plurality of branch instructions executed during a first time period. The method may also include initiating, during a second time period, the mode of speculative prediction of outcomes of the one or more branch instructions, wherein the mode of the speculative prediction is selected based, at least in part, on the criterion.