Patents Assigned to Advanced Semiconductor Engineering, Inc.
  • Method for manufacturing a semiconductor package
    Patent number: 11756926
    Abstract: A method for manufacturing a semiconductor package includes: (a) providing a substrate structure, wherein the substrate structure includes a chip attach area, a bottom area opposite to the chip attach area, a lower side rail surrounding the bottom area, a first lower structure and a second lower structure, wherein the first lower structure is disposed in a first lower region of the lower side rail, and a second lower occupancy ratio is greater than a first lower occupancy ratio; (b) attaching at least one semiconductor chip to the chip attach area; and (c) forming an encapsulant to cover the at least one semiconductor chip.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shun Sing Liao
  • Semiconductor package structure
    Patent number: 11756927
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Chi Lee, Jyan-Ann Hsia
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11756904
    Abstract: A semiconductor device package includes a substrate, a reflector, a radiator and a first director. The reflector is disposed on a surface of the substrate. The radiator is disposed over the reflector. The first director is disposed over the radiator. The reflector, the radiator and the first director have different elevations with respect to the surface of the substrate. The radiator and the first director define an antenna.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 12, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Cheng-Lin Ho, Yu-Lin Shih, Shih-Chun Li
  • Electronic structure, electronic package structure and method of manufacturing electronic device
    Patent number: 11749593
    Abstract: An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 5, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Shun-Tsat Tu
  • Package substrate and method for manufacturing the same
    Patent number: 11749619
    Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 5, 2023
    Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
  • ELECTRONIC DEVICE
    Publication number: 20230275000
    Abstract: An electronic device is provided. The electronic device includes an electronic component and a heat dissipation structure. The electronic component has a passive surface and a plurality of conductive vias exposed from the passive surface. The heat dissipation structure is disposed on the passive surface and configured to transmit a plurality of independent powers to the conductive vias through the passive surface.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Chieh HUNG, Hung-Chun KUO
  • ELECTRONIC DEVICE
    Publication number: 20230274998
    Abstract: An electronic device is disclosed. The electronic device includes an active component, a power regulating component disposed on the active component, and a patterned conductive element disposed between the active component and the power regulating component. The patterned conductive element is configured to provide one or more heat dissipation paths for the active component and to provide a power path between the active component and the power regulating component.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Chih PAN, Hung-Chun KUO
  • Semiconductor device packages and methods of manufacturing the same
    Patent number: 11742324
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 29, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Semiconductor device package and method of manufacturing the same
    Patent number: 11744024
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 29, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Hung Chen, Yung I Yeh, Chang-Lin Yeh, Sheng-Yu Chen
  • WIRING STRUCTURE
    Publication number: 20230268264
    Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Ting Wei HSU
  • ELECTRONIC DEVICE
    Publication number: 20230268293
    Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a power regulating structure configured to provide a first power to the first electronic component. The power regulating structure includes a first component and a second component at least partially overlapped with the first component from a top view.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Pao-Nan LEE, Chen-Chao WANG, Chang Chi LEE
  • SEMICONDUCTOR DEVICE PACKAGE
    Publication number: 20230268638
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first antenna pattern disposed at a first elevation and a second antenna pattern disposed at a second elevation different from the first elevation. The first antenna pattern and the second antenna pattern define an air cavity. The semiconductor device package also includes a circuit layer. The air cavity is between the first antenna pattern, the second antenna pattern, and the circuit layer.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yu HO, Meng-Wei HSIEH
  • ELECTRONIC DEVICE WITH FRAME COMPONENT
    Publication number: 20230268254
    Abstract: An electronic device is provided. The electronic device includes a circuit pattern layer. The circuit pattern layer includes a first surface, a second surface recessed with respect to the first surface; and a third surface recessed with respect to the first surface and adjacent to and spaced apart from the second surface. The second surface and the third surface are mis-aligned with each other.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Hui-Chen HSU
  • SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    Publication number: 20230268314
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shan-Bo WANG, Chin-Li KAO, An-Hsuan HSU
  • ELECTRONIC DEVICE
    Publication number: 20230269866
    Abstract: An electronic device is provided. The electronic device includes a carrier, a first electronic component, a second electronic component, and an encapsulant. The first electronic component is disposed at a first side of the carrier. The second electronic component is disposed at a second side of the carrier opposite to the first side. The encapsulant encapsulates the first electronic component and has an uneven thickness. The encapsulant is configured to reduce a warpage of the carrier.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Jhen CIOU, Jenchun CHEN, Chang-Fu LU, Pai-Sheng SHIH
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20230268295
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a carrier having a first side and a second side adjacent to the first side. The semiconductor device also includes a first antenna adjacent to the first side and configured to operate at a first frequency and a second antenna adjacent to the second side and configured to operate at a second frequency different from the first frequency. An method of manufacturing a semiconductor device is also provided.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jenchun CHEN, Shyue-Long LOUH
  • Antenna device and method for manufacturing the same
    Patent number: 11735830
    Abstract: An antenna device and a method for manufacturing the same are provided. The antenna device includes a carrier and an antenna element. The carrier includes a plurality of pads and has a surface exposing the pads. The antenna element is disposed above the pads. A lateral surface of one of the pads is farther from a central axis of the antenna element substantially perpendicular to the surface than from a lateral surface of the antenna element.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 22, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jenchun Chen, Chang-Fu Lu
  • Package structure and testing method
    Patent number: 11733294
    Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 22, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chen-Chao Wang, Tsung-Tang Tsai, Chih-Yi Huang
  • Substrate structure, package structure and method for manufacturing electronic package structure
    Patent number: 11735433
    Abstract: A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: August 22, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt
  • ELECTRONIC STRUCTURE
    Publication number: 20230260957
    Abstract: An electronic structure includes a packaging structure, a circuit pattern structure, an underfill and a protrusion structure. The circuit pattern structure is disposed over the packaging structure. A gap is between the circuit pattern structure and the packaging structure. The underfill is disposed in the gap. The protrusion structure is disposed in the gap, and is configured to facilitate the distributing of the underfill in the gap.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Po-Jen CHENG, Wei-Jen WANG, Fu-Yuan CHEN